From 65316ec9262e1cc10fdc7215f2d3ead579d1e258 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Sep 2021 10:06:20 -0700 Subject: [PATCH] abc9: holes module to instantiate cells with NEW_ID (#2992) * Add testcase * holes module to instantiate cells with NEW_ID --- passes/techmap/abc9_ops.cc | 2 +- tests/techmap/bug2759.ys | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 tests/techmap/bug2759.ys diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index c3eaa70d1..a2f1dd955 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -812,7 +812,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) auto &holes_cell = r.first->second; if (r.second) { if (box_module->get_bool_attribute(ID::whitebox)) { - holes_cell = holes_module->addCell(cell->name, cell->type); + holes_cell = holes_module->addCell(NEW_ID, cell->type); if (box_module->has_processes()) Pass::call_on_module(design, box_module, "proc"); diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys new file mode 100644 index 000000000..05699bef8 --- /dev/null +++ b/tests/techmap/bug2759.ys @@ -0,0 +1,14 @@ +read_verilog -specify < o) = 1; +endspecify +assign o = ^i; +endmodule + +module top(input [1:0] i, output o); +box i1(i, o); +endmodule +EOT +abc9 -lut 4 -- 2.30.2