From 6544cb5289824d813ab580746ab2748da6fa59e5 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sat, 16 Nov 2019 10:55:40 +0000 Subject: [PATCH] [AArch64] Replace SVE_PARTIAL with SVE_PARTIAL_I Another renaming, this time to make way for partial/unpacked float modes. 2019-11-16 Richard Sandiford gcc/ * config/aarch64/iterators.md (SVE_PARTIAL): Rename to... (SVE_PARTIAL_I): ...this. * config/aarch64/aarch64-sve.md: Apply the above renaming throughout. From-SVN: r278339 --- gcc/ChangeLog | 6 ++++++ gcc/config/aarch64/aarch64-sve.md | 16 ++++++++-------- gcc/config/aarch64/iterators.md | 8 ++++---- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fbf188089cf..b7e46cf9b78 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-11-16 Richard Sandiford + + * config/aarch64/iterators.md (SVE_PARTIAL): Rename to... + (SVE_PARTIAL_I): ...this. + * config/aarch64/aarch64-sve.md: Apply the above renaming throughout. + 2019-11-16 Richard Sandiford * config/aarch64/iterators.md (SVE_ALL): Rename to... diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 88eaaa37c03..5b71ab029b3 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2818,33 +2818,33 @@ ;; ------------------------------------------------------------------------- ;; Predicated SXT[BHW]. -(define_insn "@aarch64_pred_sxt" +(define_insn "@aarch64_pred_sxt" [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w") (unspec:SVE_FULL_HSDI [(match_operand: 1 "register_operand" "Upl") (sign_extend:SVE_FULL_HSDI - (truncate:SVE_PARTIAL + (truncate:SVE_PARTIAL_I (match_operand:SVE_FULL_HSDI 2 "register_operand" "w")))] UNSPEC_PRED_X))] "TARGET_SVE && (~ & ) == 0" - "sxt\t%0., %1/m, %2." + "sxt\t%0., %1/m, %2." ) ;; Predicated SXT[BHW] with merging. -(define_insn "@aarch64_cond_sxt" +(define_insn "@aarch64_cond_sxt" [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w, ?&w, ?&w") (unspec:SVE_FULL_HSDI [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (sign_extend:SVE_FULL_HSDI - (truncate:SVE_PARTIAL + (truncate:SVE_PARTIAL_I (match_operand:SVE_FULL_HSDI 2 "register_operand" "w, w, w"))) (match_operand:SVE_FULL_HSDI 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] UNSPEC_SEL))] "TARGET_SVE && (~ & ) == 0" "@ - sxt\t%0., %1/m, %2. - movprfx\t%0., %1/z, %2.\;sxt\t%0., %1/m, %2. - movprfx\t%0, %3\;sxt\t%0., %1/m, %2." + sxt\t%0., %1/m, %2. + movprfx\t%0., %1/z, %2.\;sxt\t%0., %1/m, %2. + movprfx\t%0, %3\;sxt\t%0., %1/m, %2." [(set_attr "movprfx" "*,yes,yes")] ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 890b3a8d721..fc27179d850 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -339,10 +339,10 @@ ;; Fully-packed SVE vector modes that have 64-bit elements. (define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF]) -;; All partial SVE modes. -(define_mode_iterator SVE_PARTIAL [VNx2QI - VNx4QI VNx2HI - VNx8QI VNx4HI VNx2SI]) +;; All partial SVE integer modes. +(define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI + VNx4HI VNx2HI + VNx2SI]) ;; Modes involved in extending or truncating SVE data, for 8 elements per ;; 128-bit block. -- 2.30.2