From 6544f8e67fd000958498e406cae7fa429d1c9dda Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 Feb 2020 13:23:14 +0000 Subject: [PATCH] separate section for meeting --- ...022_2020feb14_openpower_eula_released.mdwn | 31 +++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/updates/022_2020feb14_openpower_eula_released.mdwn b/updates/022_2020feb14_openpower_eula_released.mdwn index 5c53bde..b70cc96 100644 --- a/updates/022_2020feb14_openpower_eula_released.mdwn +++ b/updates/022_2020feb14_openpower_eula_released.mdwn @@ -100,11 +100,38 @@ actually release actual free software which actually improves actual real-world infrastructure for the benefit of EU Citizens (and incidentally the rest of the world) is a bit of an eye-opener. -Also it was fantastic to meet Staf, and talk to him about the upcoming +I had a brief chat with the person from the EU Commission. He was +delighted to be able to see the sheer number of people involved and being +sponsored by NLNet. I had an opportunity to ask him about the anti-trust +aspects of the RISC-V Foundation's ongoing intransigent behaviour. +He initially expressed puzzlement and some concern, because the EU is +funding quite a lot of RISC-V projects, and none of them had any issues. +I asked him a very simple question: "how many of those projects are +simply *implementing* existing RISC-V Standards?", and he replied, "all +of them". I then asked, "how many of those projects are *innovating*, +developing alternative extensions to RISC-V?" That was the point at which +he understood the extent of the problem, and how the RISC-V Foundation - +and its members - are at risk of violating EU anti-trust legislation. + +oops. + +# Meeting other LibreSOC people + +It was fantastic to meet Staf, and talk to him about the upcoming test chip that he'll be doing. He will be including an SR-Latch cell for -us, because it saves such a vast number of gates. There were several other +us, because it saves such a vast number of gates in the Dependency +Matrices if we use a D-Flip-Flop: 50,000 gates if we use an SR-Latch, +and a *quarter of a million* if we use a DFF. + +There were several other people we met, including one who can help us to develop a [BSP](http://bugs.libre-riscv.org/show_bug.cgi?id=164) (Board Support Package). +Also we got a chance to talk to several other people with cross-over skillsets. + +This alone was worth the time to go to FOSDEM, this year. Now what +we have to do is make sure to plan properly in advance, to put in some +papers at appropriate conferences. We really need to organise a proper +conference where everyone meets up. # New members -- 2.30.2