From 6559e5b12a251f3bd5b55fe0373fcb5828c960dc Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 22:25:56 +0100
Subject: [PATCH] add images

---
 simple_v_extension/simple_v_chennai_2018.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index c100bdf41..b2e3c92c0 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -241,7 +241,7 @@
    \item Predication in INT regs as a BIT field (max VL=XLEN)
    \item Minimum VL must be Num Regs - 1 (all regs single LD/ST)
    \item SV may condense sparse Vecs: RVV lets ALU do predication
-   \item NO ZEROING: non-predicated elements are skipped
+   \item Choice to Zero or skip non-predicated elements
   \end{itemize}
 }
 
-- 
2.30.2