From 657c2daa50055c64d1059391b4c788961d8158d0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 27 Apr 2022 16:19:23 +0100 Subject: [PATCH] --- openpower/sv/biginteger/analysis.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 55e7ad6c8..719755e34 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -282,8 +282,8 @@ With effectively 5 operands (3 in, 2 out) some compromises are needed. A little though gives a useful workaround: two modes, controlled by a single bit in `RM.EXTRA`, determine whether the 5th register is set to RC or whether to RT+VL. This then leaves only -4 registers to qualify as scalar/vector, and this can use four -EXTRA2 designators which fits into the available space. +4 registers to qualify as scalar/vector, which can use four +EXTRA2 designators and fits into the available 9-bit space. RS=RT+VL Mode: -- 2.30.2