From 6589a9d16e61bd64d8282a3b28b13316cc4fcc1c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 26 Oct 2021 10:13:34 +0100 Subject: [PATCH] add openpower2021 talk latex --- conferences/openpower2021/openpower_2021.tex | 141 +++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 conferences/openpower2021/openpower_2021.tex diff --git a/conferences/openpower2021/openpower_2021.tex b/conferences/openpower2021/openpower_2021.tex new file mode 100644 index 000000000..138a6ef08 --- /dev/null +++ b/conferences/openpower2021/openpower_2021.tex @@ -0,0 +1,141 @@ +\documentclass[slidestop]{beamer} +\usepackage{beamerthemesplit} +\usepackage{graphics} +\usepackage{pstricks} + +\graphicspath{{./}} + +\title{The Libre-SOC Hybrid 3D CPU} +\author{Luke Kenneth Casson Leighton} + + +\begin{document} + +\frame{ + \begin{center} + \huge{The Libre-SOC Hybrid 3D CPU}\\ + \vspace{32pt} + \Large{Draft SVP64 in-place Matrix Multiply}\\ + \Large{and FFT / DCT for the Power ISA}\\ + \vspace{24pt} + \Large{OpenPOWER Summit 2021}\\ + \vspace{16pt} + \large{Sponsored by NLnet's PET Programme}\\ + \vspace{6pt} + \large{28th Oct 2021} + \end{center} +} + + +\frame{\frametitle{} + +\vspace{15pt} + + \begin{itemize} + \item \vspace{15pt} + \item \vspace{15pt} + \item \vspace{15pt} + \end{itemize} +} + +\frame{\frametitle{Overview of Libre-SOC goals} + +\vspace{15pt} + + \begin{itemize} + \item To create power-efficient mass-volume products\vspace{15pt} + \item To leverage the OpenPOWER ecosystem to do so\vspace{15pt} + \item To be entirely transparent for Security reasons\vspace{15pt} + \item To empower businesses to bring Secure transparent\\ + mass-volume products to market\vspace{15pt} + \end{itemize} +} + +\frame{\frametitle{Overview of SVP64 goals} + +\vspace{15pt} + + \begin{itemize} + \item High performance and high performance/watt\vspace{15pt} + \item Reduced code density (reduced I-Cache usage)\\ + https://arxiv.org/abs/2002.10143 - 3.5x power reduction\vspace{8pt} + \item Remain accessible for assembler writers and compilers alike\vspace{15pt} + \item Introduce true Vectorisation to the Power ISA\\ + (VSX is Packed SIMD)\vspace{8pt} + \item Be adopted via the external OPF ISA WG RFC process\\ + (not: be a non-official custom extension. proprietary\\ + custom extensions conflict with mass-volume adoption)\vspace{15pt} + \end{itemize} +} + + + +%%\frame{\frametitle{nmigen PowerISA Decoder} + +%%\begin{center} +%%\includegraphics[width=0.55\textwidth]{2020-09-09_21-04.png} +%%\end{center} + +%%} + +\begin{frame}[fragile] +\frametitle{Reminder of Simple-V} + +\begin{semiverbatim} +Greatly simplified (like x86 "REP" instruction): + +  for (i = 0; i < VL; i++) +    ireg[RT+i] <= ireg[RA+i] + ireg[RB+i]; + +function op\_add(rd, rs1, rs2, predr) # add not VADD! +  int i, id=0, irs1=0, irs2=0; +  for (i = 0; i < VL; i++) +   if (ireg[predr] & 1<