From 65a4d55a9ff12b44655803da10112d3b1b42ce13 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 10 Oct 2016 17:39:43 +0200 Subject: [PATCH] radeonsi: don't invalidate VMEM L1 for memory barriers for index buffers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index ddf6cfe14de..34f3ed7264b 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3366,6 +3366,7 @@ static void si_texture_barrier(struct pipe_context *ctx) SI_CONTEXT_CS_PARTIAL_FLUSH; } +/* This only ensures coherency for shader image/buffer stores. */ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) { struct si_context *sctx = (struct si_context *)ctx; @@ -3392,9 +3393,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) } if (flags & PIPE_BARRIER_INDEX_BUFFER) { - sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; - - /* Indices are read through TC L2 since VI. */ + /* Indices are read through TC L2 since VI. + * L1 isn't used. + */ if (sctx->screen->b.chip_class <= CIK) sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; } -- 2.30.2