From 65ad441b8a6aa9fc4a1756e19e3f702c9e1a7f98 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Jun 2020 20:21:12 +0100 Subject: [PATCH] make Memory accessible via TestSRAMBareLoadStoreUnit --- src/soc/bus/test/test_minerva.py | 2 +- src/soc/fu/compunits/test/test_compunit.py | 11 ++++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py index c813a77c..d9c7f101 100644 --- a/src/soc/bus/test/test_minerva.py +++ b/src/soc/bus/test/test_minerva.py @@ -11,7 +11,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): m = super().elaborate(platform) comb = m.d.comb # small 16-entry Memory - memory = Memory(width=self.data_wid, depth=16) + self.mem = memory = Memory(width=self.data_wid, depth=16) m.submodules.sram = sram = SRAM(memory=memory, granularity=8, features={'cti', 'bte', 'err'}) dbus = self.dbus diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 7b4c41cf..3e5c3790 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -103,8 +103,13 @@ def get_inp_indexed(cu, inp): res[i] = inp[wrop] return res +def get_l0_mem(l0): # BLECH! + if hasattr(l0.pimem, 'lsui'): + return l0.pimem.lsui.mem + return l0.pimem.mem.mem + def setup_test_memory(l0, sim): - mem = l0.pimem.mem.mem + mem = get_l0_mem(l0) print ("before, init mem", mem.depth, mem.width, mem) for i in range(mem.depth): data = sim.mem.ld(i*8, 8, False) @@ -120,7 +125,7 @@ def setup_test_memory(l0, sim): def check_sim_memory(dut, l0, sim, code): - mem = l0.pimem.mem.mem + mem = get_l0_mem(l0) print ("sim mem dump") for k, v in sim.mem.mem.items(): print (" %6x %016x" % (k, v)) @@ -161,7 +166,7 @@ class TestRunner(FHDLTestCase): from soc.experiment.l0_cache import TstL0CacheBuffer m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64, addrwid=3, - ifacetype='test_bare_wb') + ifacetype='testpi') pi = l0.l0.dports[0] m.submodules.cu = cu = self.fukls(pi, awid=3) m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel -- 2.30.2