From 65afab8694c4fb8b48f590068f59791745aab717 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Nov 2021 10:36:30 +0000 Subject: [PATCH] update license and attribution in fu_reg_matrix.py --- src/soc/scoreboard/fu_reg_matrix.py | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/src/soc/scoreboard/fu_reg_matrix.py b/src/soc/scoreboard/fu_reg_matrix.py index 35fcac0d..7c35c357 100644 --- a/src/soc/scoreboard/fu_reg_matrix.py +++ b/src/soc/scoreboard/fu_reg_matrix.py @@ -1,13 +1,11 @@ -from nmigen.compat.sim import run_simulation -from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Cat, Repl - -from soc.scoreboard.dependence_cell import DependencyRow -from soc.scoreboard.fu_wr_pending import FU_RW_Pend -from soc.scoreboard.reg_select import Reg_Rsv -from soc.scoreboard.global_pending import GlobalPending +# (DO NOT REMOVE THESE NOTICES) +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2019, 2020, 2021 Luke Kenneth Casson Leighton +# Part of the Libre-SOC Project. +# Sponsored by NLnet EU Grant No: 825310 and 825322 +# Sponsored by NGI POINTER EU Grant No: 871528 -""" +"""Mitch Alsup 6600 Dependency Matrices: Function Units to Registers (FU-REGs) 6600 Dependency Table Matrix inputs / outputs --------------------------------------------- @@ -25,6 +23,16 @@ from soc.scoreboard.global_pending import GlobalPending """ +from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil +from nmigen import Module, Signal, Elaboratable, Cat, Repl + +from soc.scoreboard.dependence_cell import DependencyRow +from soc.scoreboard.fu_wr_pending import FU_RW_Pend +from soc.scoreboard.reg_select import Reg_Rsv +from soc.scoreboard.global_pending import GlobalPending + + class FURegDepMatrix(Elaboratable): """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26 """ @@ -136,8 +144,7 @@ class FURegDepMatrix(Elaboratable): # accumulate cell fwd outputs for dest/src1/src2 src_fwd_o.append(dc.src_fwd_o[i][rn]) # connect cell fwd outputs to FU Vector in [Cat is gooood] - m.d.comb += [fup.src_fwd_i[i].eq(Cat(*src_fwd_o)), - ] + m.d.comb += fup.src_fwd_i[i].eq(Cat(*src_fwd_o)) # accumulate FU Vector outputs rd_src_pend.append(fup.reg_rd_src_pend_o[i]) # ... and output them from this module (vertical, width=FUs) -- 2.30.2