From 65b0692844ab0ff23adeb50f3507a6ac32c52cf9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 12 Jan 2022 11:21:40 +0000 Subject: [PATCH] fix issue with d_valid in dcache, was not being set properly --- src/soc/experiment/dcache.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index a828e3c3..374297ba 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -741,13 +741,14 @@ class DCache(Elaboratable): with m.If((~r1.full & ~d_in.hold) | ~r0_full): sync += r0.eq(r) sync += r0_full.eq(r.req.valid) - # Sample data the cycle after a request comes in from loadstore1. - # If another request has come in already then the data will get - # put directly into req.data below. - with m.If(r0.req.valid & ~r.req.valid & ~r0.d_valid & - ~r0.mmu_req): - sync += r0.req.data.eq(d_in.data) - sync += r0.d_valid.eq(1) + # Sample data the cycle after a request comes in from loadstore1. + # If another request has come in already then the data will get + # put directly into req.data below. + sync += r0.d_valid.eq(0) + with m.If(r0.req.valid & ~r.req.valid & ~r0.d_valid & + ~r0.mmu_req): + sync += r0.req.data.eq(d_in.data) + sync += r0.d_valid.eq(1) with m.If(d_in.valid): m.d.sync += Display(" DCACHE req cache " "virt %d addr %x data %x ld %d", -- 2.30.2