From 65d219821c0efb3938dd5f4f00289be4ba09d3ec Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Jun 2020 13:51:52 +0100 Subject: [PATCH] experimenting with CR, not quite right --- src/soc/simple/test/test_core.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 0cb97a59..dae9267e 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -81,9 +81,12 @@ class TestRunner(FHDLTestCase): # set up CR regfile, "direct" write across all CRs cr = test.cr + #cr = int('{:32b}'.format(cr)[::-1], 2) print ("cr reg", hex(cr)) for i in range(8): + #j = 7-i cri = (cr>>(i*4)) & 0xf + #cri = int('{:04b}'.format(cri)[::-1], 2) print ("cr reg", hex(cri), i, core.regs.cr.regs[i].reg.shape()) yield core.regs.cr.regs[i].reg.eq(cri) @@ -171,10 +174,10 @@ if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() suite.addTest(TestRunner(CRTestCase.test_data)) - suite.addTest(TestRunner(ShiftRotTestCase.test_data)) - suite.addTest(TestRunner(LogicalTestCase.test_data)) - suite.addTest(TestRunner(ALUTestCase.test_data)) - suite.addTest(TestRunner(BranchTestCase.test_data)) + #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) + #suite.addTest(TestRunner(LogicalTestCase.test_data)) + #suite.addTest(TestRunner(ALUTestCase.test_data)) + #suite.addTest(TestRunner(BranchTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2