From 65e1dd9ef1d661928a2ed4125fb9d544c48da969 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Mar 2021 13:21:25 +0000 Subject: [PATCH] add predication read ports (CR and INT) --- src/soc/regfile/regfiles.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index aec56e44..2512d3ae 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -77,6 +77,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray): self.r_ports = {'ra': self.read_port("src1"), 'rb': self.read_port("src2"), 'rc': self.read_port("src3"), + 'pred': self.read_port("pred"), # for predicate mask 'dmi': self.read_port("dmi")} # needed for Debug (DMI) @@ -129,6 +130,7 @@ class CRRegs(VirtualRegPort): 'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines) 'full_cr_dbg': self.full_rd2, # for DMI + 'cr_pred': self.read_port("cr_pred"), # for predicate 'cr_a': self.read_port("src1"), 'cr_b': self.read_port("src2"), 'cr_c': self.read_port("src3")} -- 2.30.2