From 65e6aefb6ffe1ac482541c66fb8bb8388b961dda Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 3 May 2022 09:24:24 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 1faad4e0d..f4bbfcc99 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -1137,6 +1137,14 @@ start from half-way into r3. The reason is that with MAXVL bring 5 and elwidth being 32, this is the 5th element offset (in 32 bit quantities) counting from r1. +*Programmer's note: accessing registers that have been placed +starting on a non-contiguous boundary (half-way along a scalar +register) can be inconvenient: REMAP can provide an offset but +it requires extra instructions to set up. A simple solution +is to ensure that MAXVL is rounded up such that the Vector +ends cleanly on a contiguous register boundary. MAXVL=6 in +the above example would achieve that* + Additional DRAFT Scalar instructions in 3-in 2-out form with an implicit 2nd destination: -- 2.30.2