From 660e6c2c127fdec06bfa428b08ab4123e37281a5 Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Wed, 16 Nov 2016 18:30:56 +0000 Subject: [PATCH] Fix ICE on empty FIQ interrupt handler on ARM 2016-11-16 Thomas Preud'homme gcc/ * config/arm/arm.md (arm_addsi3): Add alternative for addition of general register with general register or ARM constant into SP register. gcc/testsuite/ * gcc.target/arm/empty_fiq_handler.c: New test. From-SVN: r242508 --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/arm.md | 13 +++++++------ gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/arm/empty_fiq_handler.c | 11 +++++++++++ 4 files changed, 28 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/empty_fiq_handler.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5d90c17021d..02a309f735f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-16 Thomas Preud'homme + + * config/arm/arm.md (arm_addsi3): Add alternative for addition of + general register with general register or ARM constant into SP + register. + 2016-11-16 Jakub Jelinek PR fortran/78299 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 761c52f4185..a4f83d67377 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -609,9 +609,9 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") - (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 @@ -621,6 +621,7 @@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + add%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 @@ -640,10 +641,10 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") (const_string "alu_sreg"))) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e095a402627..4c274d73148 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2016-11-16 Thomas Preud'homme + + * gcc.target/arm/empty_fiq_handler.c: New test. + 2016-11-16 Jakub Jelinek PR fortran/78299 diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c new file mode 100644 index 00000000000..bbcfd0e32f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ + +/* Below code used to trigger an ICE due to missing constraints for + sp = fp + cst pattern. */ + +void fiq_handler (void) __attribute__((interrupt ("FIQ"))); + +void +fiq_handler (void) +{ +} -- 2.30.2