From 661f00ea3726c971df8a8acf3b8da713e07fdb37 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Jun 2022 15:26:53 +0100 Subject: [PATCH] clarify primer --- svp64-primer/summary.tex | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index a2fc94f0c..99fcd8b59 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -110,6 +110,9 @@ the number of instructions increase: \item Documentation of the ISA \item Manual coding and optimisation \item Time to support the platform + \item Compilance Suite development and testing + \item Protracted Variable-Length encoding (x86) severely compromises + Multi-issue decoding \end{itemize} \subsection{Simple Vectorisation} @@ -124,9 +127,9 @@ Main design principles \begin{itemize} \item Introduce by implementing on top of existing Power ISA \item Effectively a \textbf{hardware for-loop}, pauses main PC, - issues multiple scalar op's - \item Preserves underlying scalar execution dependencies as - the for-loop had been expanded as actual scalar instructions + issues multiple scalar operations + \item Preserves underlying scalar execution dependencies as if + the for-loop had been expanded into actual scalar instructions ("preserving Program Order") \item Augments existing instructions by adding "tags" - provides Vectorisation "context" rather than adding new opcodes. @@ -135,7 +138,8 @@ Main design principles advantage in the vector space (see \ref{subsubsec:add_to_pow_isa}) \item Aimed at Supercomputing: avoids creating significant \textit{sequential dependency hazards}, allowing \textbf{high - performance superscalar microarchitectures} to be deployed. + performance multi-issue superscalar microarchitectures} to be + leveraged. \end{itemize} Advantages include: -- 2.30.2