From 6639ab0c1689a429d503b94b3c656ae58ad54d95 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 12 Feb 2022 15:54:33 +0000 Subject: [PATCH] add larger PLL reset countdown to give ULX3S a chance to stabilise --- fpga/top-generic.vhdl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl index 8bff5bb..14ffabe 100644 --- a/fpga/top-generic.vhdl +++ b/fpga/top-generic.vhdl @@ -9,6 +9,7 @@ entity toplevel is MEMORY_SIZE : positive := (384*1024); RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; + PLL_RESET_BITS : positive := 18; CLK_INPUT : positive := 100000000; CLK_FREQUENCY : positive := 100000000; HAS_FPU : boolean := true; @@ -41,7 +42,8 @@ begin reset_controller: entity work.soc_reset generic map( - RESET_LOW => RESET_LOW + RESET_LOW => RESET_LOW, + PLL_RESET_BITS => PLL_RESET_BITS ) port map( ext_clk => ext_clk, -- 2.30.2