From 6645c20c2378534adfe0266d680d62abc51527f7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Dec 2021 01:08:11 +0000 Subject: [PATCH] whoops error in accessing icache.ibus which is an intermediary set of signals --- src/openpower/test/runner.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index cc91b75d..333bb117 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -483,7 +483,7 @@ class TestRunnerBase(FHDLTestCase): default_mem = self.rom sim.add_sync_process(wrap(wb_get(dcache.bus, default_mem, "DCACHE"))) - sim.add_sync_process(wrap(wb_get(icache.ibus, + sim.add_sync_process(wrap(wb_get(icache.bus, default_mem, "ICACHE"))) with sim.write_vcd("issuer_simulator.vcd"): -- 2.30.2