From 664940950309883d87c67c3187fc93d824494a38 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 17 Dec 2020 11:56:40 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 35 +++++++++++++++++++---------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index a21777b34..7f55cc2a3 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -63,7 +63,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd). * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest) -* `RM-2P1S1D` Twin Predication (src=1, dest=1) +* `RM-2P-1S1D` Twin Predication (src=1, dest=1) ## RM-1P-3S1D @@ -166,7 +166,7 @@ algorithm for original version: 2 bit version -(**TODO, i simply cannot interpret the names, they have absolutely zero meaning to me so i have no idea how to fill in the table. this is a bad sign, indicative that the names have to go, to be replaced by something xlear snd obvious**) +(**TODO, i simply cannot interpret the names, they have absolutely zero meaning to me so i have no idea how to fill in the table. this is a bad sign, indicative that the names have to go, to be replaced by something clear and obvious**) | R\*_EXTRA2 | Mode | CR Register | Int/FP
Register | |-----------|---------|---------------|---------------------| @@ -198,16 +198,27 @@ Default behaviour is set to 0b00 so that zeros follow the convention of "npt doi Only when elwidth is nonzero is the element width overridden to the explicitly required value. -| Op Kind | Value | Mnemonic | Description | -|---------|-------|----------------|------------------------------------| -| Integer | 00 | DEFAULT | default behaviour for operation | -| Integer | 01 | `ELWIDTH=b` | Byte: 8-bit integer | -| Integer | 10 | `ELWIDTH=h` | Halfword: 16-bit integer | -| Integer | 11 | `ELWIDTH=w` | Word: 32-bit integer | -| FP | 00 | DEFAULT | default behaviour for FP operation | -| FP | 01 | `ELWIDTH=bf16` (rsvd) | Reserved for [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) | -| FP | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point | -| FP | 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point | +Integer Registers: + +| Value | Mnemonic | Description | +|-------|----------------|------------------------------------| +| 00 | DEFAULT | default behaviour for operation | +| 01 | `ELWIDTH=b` | Byte: 8-bit integer | +| 10 | `ELWIDTH=h` | Halfword: 16-bit integer | +| 11 | `ELWIDTH=w` | Word: 32-bit integer | + +FP Registers: + +| Value | Mnemonic | Description | +|-------|----------------|------------------------------------| +| 00 | DEFAULT | default behaviour for FP operation | +| 01 | `ELWIDTH=bf16` (rsvd) | Reserved for [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) | +| 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point | +| 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point | + +CR Registers: + +TODO ## SUBVL Encoding -- 2.30.2