From 6649d3e990e22e5609fa194a503f7813aff3f553 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Sep 2020 09:46:00 +0100 Subject: [PATCH] add extra "modes" to PortInterface --- src/soc/experiment/pimem.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 3fac8cb6..89ba7714 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -113,6 +113,12 @@ class PortInterface(RecordObject): self.ld = Data(regwid, "ld_data_o") # ok to be set by L0 Cache/Buf self.st = Data(regwid, "st_data_i") # ok to be set by CompUnit + # additional "modes" + self.dcbz = Signal() # data cache block zero request + self.nc = Signal() # no cacheing + self.virt_mode = Signal() # virtual mode + self.priv_mode = Signal() # privileged mode + def connect_port(self, inport): print("connect_port", self, inport) return [self.is_ld_i.eq(inport.is_ld_i), -- 2.30.2