From 664b4bcb3ac2e4c688707677def1cb6b4075ea7b Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 13 Jan 2019 08:51:49 +0000 Subject: [PATCH] hdl.dsl: cases wider than switch test value are unreachable. In 3083c1d6 they were erroneously fixed via truncation. --- nmigen/hdl/dsl.py | 8 +++++--- nmigen/test/test_hdl_dsl.py | 6 ++---- nmigen/test/tools.py | 10 ++++++---- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index de0231b..918e8e3 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -219,17 +219,19 @@ class Module(_ModuleBuilderRoot): if isinstance(value, str) and len(value) != len(switch_data["test"]): raise SyntaxError("Case value '{}' must have the same width as test (which is {})" .format(value, len(switch_data["test"]))) + omit_case = False if isinstance(value, int) and bits_for(value) > len(switch_data["test"]): warnings.warn("Case value '{:b}' is wider than test (which has width {}); " - "comparison will be made against truncated value" + "comparison will never be true" .format(value, len(switch_data["test"])), SyntaxWarning, stacklevel=3) - value &= (1 << len(switch_data["test"])) - 1 + omit_case = True try: _outer_case, self._statements = self._statements, [] self._ctrl_context = None yield self._flush_ctrl() - switch_data["cases"][value] = self._statements + if not omit_case: + switch_data["cases"][value] = self._statements finally: self._ctrl_context = "Switch" self._statements = _outer_case diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 3e3df1d..31753fd 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -289,14 +289,12 @@ class DSLTestCase(FHDLTestCase): pass with self.assertWarns(SyntaxWarning, msg="Case value '10110' is wider than test (which has width 4); comparison " - "will be made against truncated value"): + "will never be true"): with m.Case(0b10110): pass self.assertRepr(m._statements, """ ( - (switch (sig w1) - (case 0110 ) - ) + (switch (sig w1) ) ) """) diff --git a/nmigen/test/tools.py b/nmigen/test/tools.py index 7c89e88..e1b1a3d 100644 --- a/nmigen/test/tools.py +++ b/nmigen/test/tools.py @@ -12,10 +12,12 @@ __all__ = ["FHDLTestCase"] class FHDLTestCase(unittest.TestCase): def assertRepr(self, obj, repr_str): obj = Statement.wrap(obj) - repr_str = re.sub(r"\s+", " ", repr_str) - repr_str = re.sub(r"\( (?=\()", "(", repr_str) - repr_str = re.sub(r"\) (?=\))", ")", repr_str) - self.assertEqual(repr(obj), repr_str.strip()) + def prepare_repr(repr_str): + repr_str = re.sub(r"\s+", " ", repr_str) + repr_str = re.sub(r"\( (?=\()", "(", repr_str) + repr_str = re.sub(r"\) (?=\))", ")", repr_str) + return repr_str.strip() + self.assertEqual(prepare_repr(repr(obj)), prepare_repr(repr_str)) @contextmanager def assertRaises(self, exception, msg=None): -- 2.30.2