From 6672ab2e3fd78d539c0efe1f13f301d5ce0aee3e Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 21 Dec 2018 01:51:18 +0000 Subject: [PATCH] back.rtlil: explicitly pad constants with zeroes. I'm not sure what exactly RTLIL does when a constant isn't as long as its bit width, and there's no reason to keep the ambiguity. --- nmigen/back/rtlil.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 433dd20..0b61268 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -353,7 +353,7 @@ class _RHSValueCompiler(_ValueCompiler): if isinstance(value.value, str): return "{}'{}".format(value.nbits, value.value) else: - return "{}'{:b}".format(value.nbits, value.value) + return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits) def on_Signal(self, value): wire_curr, wire_next = self.s.resolve(value) -- 2.30.2