From 667408b889e2bf5f103340c2deeb04c4d99cb75b Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Fri, 29 Apr 2016 16:34:10 -0700 Subject: [PATCH] i965: Merge inst_info and opcode_desc tables. I merged opcode_desc into inst_info (instead of the other way around) because inst_info was sorted by opcode number. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 7 -- src/mesa/drivers/dri/i965/brw_disasm.c | 74 ----------- src/mesa/drivers/dri/i965/brw_eu.c | 132 ++++++++++---------- src/mesa/drivers/dri/i965/brw_eu.h | 7 +- src/mesa/drivers/dri/i965/brw_eu_validate.c | 2 +- 5 files changed, 73 insertions(+), 149 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e449982bfaa..7468dfadb35 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1794,13 +1794,6 @@ bool brw_lower_texture_gradients(struct brw_context *brw, struct exec_list *instructions); bool brw_do_lower_unnormalized_offset(struct exec_list *instructions); -struct opcode_desc { - char *name; - int nsrc; - int ndst; -}; - -extern const struct opcode_desc opcode_descs[128]; extern const char * const conditional_modifier[16]; extern const char *const pred_ctrl_align16[16]; diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 9806c106c5c..17784198c69 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -30,80 +30,6 @@ #include "brw_inst.h" #include "brw_eu.h" -const struct opcode_desc opcode_descs[128] = { - [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_MOVI] = { .name = "movi", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1 }, - - [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 }, - - [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CSEL] = { .name = "csel", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1 }, - [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1 }, - - [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_SENDS] = { .name = "sends", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SENDSC] = { .name = "sendsc", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ILLEGAL] = { .name = "illegal", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_NENOP] = { .name = "nenop", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_IF] = { .name = "if", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 0, .ndst = 0 }, - // [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 }, - // [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 }, - // [BRW_OPCODE_MREST] = { .name = "mrest", .nsrc = 1, .ndst = 1 }, - // [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 0, .ndst = 0 }, -}; - static bool has_jip(const struct brw_device_info *devinfo, enum opcode opcode) { diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c index 80ce98e10e3..102e4ca6088 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.c +++ b/src/mesa/drivers/dri/i965/brw_eu.c @@ -355,102 +355,102 @@ enum gen { #define GEN_GE(gen) (~((gen) - 1) | gen) #define GEN_LE(gen) (((gen) - 1) | gen) -const struct inst_info inst_info[128] = { +const struct opcode_desc opcode_descs[128] = { [BRW_OPCODE_ILLEGAL] = { - .gens = GEN_ALL, + .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_MOV] = { - .gens = GEN_ALL, + .name = "mov", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_SEL] = { - .gens = GEN_ALL, + .name = "sel", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_MOVI] = { - .gens = GEN_GE(GEN45), + .name = "movi", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45), }, [BRW_OPCODE_NOT] = { - .gens = GEN_ALL, + .name = "not", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_AND] = { - .gens = GEN_ALL, + .name = "and", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_OR] = { - .gens = GEN_ALL, + .name = "or", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_XOR] = { - .gens = GEN_ALL, + .name = "xor", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_SHR] = { - .gens = GEN_ALL, + .name = "shr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_SHL] = { - .gens = GEN_ALL, + .name = "shl", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, /* BRW_OPCODE_DIM / BRW_OPCODE_SMOV */ /* Reserved - 11 */ [BRW_OPCODE_ASR] = { - .gens = GEN_ALL, + .name = "asr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, /* Reserved - 13-15 */ [BRW_OPCODE_CMP] = { - .gens = GEN_ALL, + .name = "cmp", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_CMPN] = { - .gens = GEN_ALL, + .name = "cmpn", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_CSEL] = { - .gens = GEN_GE(GEN8), + .name = "csel", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8), }, [BRW_OPCODE_F32TO16] = { - .gens = GEN7 | GEN75, + .name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75, }, [BRW_OPCODE_F16TO32] = { - .gens = GEN7 | GEN75, + .name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75, }, /* Reserved - 21-22 */ [BRW_OPCODE_BFREV] = { - .gens = GEN_GE(GEN7), + .name = "bfrev", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_BFE] = { - .gens = GEN_GE(GEN7), + .name = "bfe", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_BFI1] = { - .gens = GEN_GE(GEN7), + .name = "bfi1", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_BFI2] = { - .gens = GEN_GE(GEN7), + .name = "bfi2", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7), }, /* Reserved - 27-31 */ [BRW_OPCODE_JMPI] = { - .gens = GEN_ALL, + .name = "jmpi", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, /* BRW_OPCODE_BRD */ [BRW_OPCODE_IF] = { - .gens = GEN_ALL, + .name = "if", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_IFF] = { /* also BRW_OPCODE_BRC */ - .gens = GEN_LE(GEN5), + .name = "iff", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5), }, [BRW_OPCODE_ELSE] = { - .gens = GEN_ALL, + .name = "else", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_ENDIF] = { - .gens = GEN_ALL, + .name = "endif", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_DO] = { /* also BRW_OPCODE_CASE */ - .gens = GEN_LE(GEN5), + .name = "do", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5), }, [BRW_OPCODE_WHILE] = { - .gens = GEN_ALL, + .name = "while", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_BREAK] = { - .gens = GEN_ALL, + .name = "break", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_CONTINUE] = { - .gens = GEN_ALL, + .name = "cont", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_HALT] = { - .gens = GEN_ALL, + .name = "halt", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, /* BRW_OPCODE_CALLA */ /* BRW_OPCODE_MSAVE / BRW_OPCODE_CALL */ @@ -458,109 +458,111 @@ const struct inst_info inst_info[128] = { /* BRW_OPCODE_PUSH / BRW_OPCODE_FORK / BRW_OPCODE_GOTO */ /* BRW_OPCODE_POP */ [BRW_OPCODE_WAIT] = { - .gens = GEN_ALL, + .name = "wait", .nsrc = 1, .ndst = 0, .gens = GEN_ALL, }, [BRW_OPCODE_SEND] = { - .gens = GEN_ALL, + .name = "send", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_SENDC] = { - .gens = GEN_ALL, + .name = "sendc", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_SENDS] = { - .gens = GEN_GE(GEN9), + .name = "sends", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9), }, [BRW_OPCODE_SENDSC] = { - .gens = GEN_GE(GEN9), + .name = "sendsc", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9), }, /* Reserved 53-55 */ [BRW_OPCODE_MATH] = { - .gens = GEN_GE(GEN6), + .name = "math", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6), }, /* Reserved 57-63 */ [BRW_OPCODE_ADD] = { - .gens = GEN_ALL, + .name = "add", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_MUL] = { - .gens = GEN_ALL, + .name = "mul", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_AVG] = { - .gens = GEN_ALL, + .name = "avg", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_FRC] = { - .gens = GEN_ALL, + .name = "frc", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_RNDU] = { - .gens = GEN_ALL, + .name = "rndu", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_RNDD] = { - .gens = GEN_ALL, + .name = "rndd", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_RNDE] = { - .gens = GEN_ALL, + .name = "rnde", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_RNDZ] = { - .gens = GEN_ALL, + .name = "rndz", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_MAC] = { - .gens = GEN_ALL, + .name = "mac", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_MACH] = { - .gens = GEN_ALL, + .name = "mach", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_LZD] = { - .gens = GEN_ALL, + .name = "lzd", .nsrc = 1, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_FBH] = { - .gens = GEN_GE(GEN7), + .name = "fbh", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_FBL] = { - .gens = GEN_GE(GEN7), + .name = "fbl", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_CBIT] = { - .gens = GEN_GE(GEN7), + .name = "cbit", .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_ADDC] = { - .gens = GEN_GE(GEN7), + .name = "addc", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_SUBB] = { - .gens = GEN_GE(GEN7), + .name = "subb", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7), }, [BRW_OPCODE_SAD2] = { - .gens = GEN_ALL, + .name = "sad2", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_SADA2] = { - .gens = GEN_ALL, + .name = "sada2", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, /* Reserved 82-83 */ [BRW_OPCODE_DP4] = { - .gens = GEN_ALL, + .name = "dp4", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_DPH] = { - .gens = GEN_ALL, + .name = "dph", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_DP3] = { - .gens = GEN_ALL, + .name = "dp3", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_DP2] = { - .gens = GEN_ALL, + .name = "dp2", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, /* Reserved 88 */ [BRW_OPCODE_LINE] = { - .gens = GEN_ALL, + .name = "line", .nsrc = 2, .ndst = 1, .gens = GEN_ALL, }, [BRW_OPCODE_PLN] = { - .gens = GEN_GE(GEN45), + .name = "pln", .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45), }, [BRW_OPCODE_MAD] = { - .gens = GEN_GE(GEN6), + .name = "mad", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6), }, [BRW_OPCODE_LRP] = { - .gens = GEN_GE(GEN6), + .name = "lrp", .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6), }, /* Reserved 93-124 */ - /* BRW_OPCODE_NENOP */ + [BRW_OPCODE_NENOP] = { + .name = "nenop", .nsrc = 0, .ndst = 0, .gens = GEN45, + }, [BRW_OPCODE_NOP] = { - .gens = GEN_ALL, + .name = "nop", .nsrc = 0, .ndst = 0, .gens = GEN_ALL, }, }; diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index a1434e4778a..a212f51b007 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -545,11 +545,14 @@ next_offset(const struct brw_device_info *devinfo, void *store, int offset) return offset + 16; } -struct inst_info { +struct opcode_desc { + char *name; + int nsrc; + int ndst; int gens; }; -extern const struct inst_info inst_info[128]; +extern const struct opcode_desc opcode_descs[128]; int gen_from_devinfo(const struct brw_device_info *devinfo); diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index b87b32e1ed7..6f55df96bde 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c +++ b/src/mesa/drivers/dri/i965/brw_eu_validate.c @@ -122,7 +122,7 @@ is_unsupported_inst(const struct brw_device_info *devinfo, const brw_inst *inst) { int gen = gen_from_devinfo(devinfo); - return (inst_info[brw_inst_opcode(devinfo, inst)].gens & gen) == 0; + return (opcode_descs[brw_inst_opcode(devinfo, inst)].gens & gen) == 0; } bool -- 2.30.2