From 668c2125280b75102e4a21220eff768c5b37f0d7 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 27 Nov 2019 17:58:42 +0000 Subject: [PATCH] back.rtlil: infer bit width for instance parameters. Otherwise, Yosys assumes it is always 32, which is often inappropriate. --- nmigen/back/rtlil.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 7806ace..9869c61 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -128,8 +128,8 @@ class _ModuleBuilder(_Namer, _BufferedBuilder, _AttrBuilder): self._append(" parameter \\{} \"{}\"\n", param, value.translate(self._escape_map)) elif isinstance(value, int): - self._append(" parameter \\{} {:d}\n", - param, value) + self._append(" parameter \\{} {}'{:b}\n", + param, bits_for(value), value) elif isinstance(value, float): self._append(" parameter real \\{} \"{!r}\"\n", param, value) -- 2.30.2