From 66b1205086ce67673ca8d2b5c4ba0bbf75f05085 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 May 2020 20:54:06 +0100 Subject: [PATCH] Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog --- 1e/23846cfcf48a20e8be52eee95a6616ff3d500d | 93 +++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 1e/23846cfcf48a20e8be52eee95a6616ff3d500d diff --git a/1e/23846cfcf48a20e8be52eee95a6616ff3d500d b/1e/23846cfcf48a20e8be52eee95a6616ff3d500d new file mode 100644 index 0000000..f104f36 --- /dev/null +++ b/1e/23846cfcf48a20e8be52eee95a6616ff3d500d @@ -0,0 +1,93 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 13 May 2020 20:54:32 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jYxSY-000068-VI; Wed, 13 May 2020 20:54:30 +0100 +Received: from lkcl.net ([217.147.94.29]) + by libre-soc.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jYxSX-000062-Df + for libre-riscv-dev@lists.libre-riscv.org; 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