From 66b85577dede3017b5c3535d0017e60d77a4c96b Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 3 Oct 2021 10:33:35 +0200 Subject: [PATCH] remove redunant pi_dcbz --- src/soc/config/test/test_pi2ls.py | 38 ++----------------------- src/soc/experiment/test/test_dcbz_pi.py | 4 +-- 2 files changed, 5 insertions(+), 37 deletions(-) diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index c9d5df38..196020b7 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -43,12 +43,13 @@ def wait_ldok(port): yield -def pi_st(port1, addr, data, datalen, msr_pr=0): +def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0): # have to wait until not busy yield from wait_busy(port1, no=False) # wait until not busy # set up a ST on the port. address first: + yield port1.is_dcbz_i.eq(is_dcbz) # reset dcbz too yield port1.is_st_i.eq(1) # indicate ST yield port1.data_len.eq(datalen) # ST length (1/2/4/8) yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real) @@ -72,40 +73,7 @@ def pi_st(port1, addr, data, datalen, msr_pr=0): yield port1.is_dcbz_i.eq(0) # reset dcbz too -# copy of pi_st -def pi_dcbz(port1, addr, msr_pr=0): - - # have to wait until not busy - yield from wait_busy(port1, no=False,debug="busy") # wait until not busy - - # set up a ST on the port. address first: - yield port1.is_st_i.eq(1) # indicate ST - yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real) - - yield port1.is_dcbz_i.eq(1) # set dcbz #FIXME - - yield port1.addr.data.eq(addr) # set address - yield port1.addr.ok.eq(1) # set ok - yield Settle() - - # guess: this is not needed - # yield from wait_addr(port1,debug="addr") # wait until addr ok - - # just write some dummy data -- remove - print("dummy write begin") - yield port1.st.data.eq(0) - yield port1.st.ok.eq(1) - yield - yield port1.st.ok.eq(0) - print("dummy write end") - - yield from wait_busy(port1, no=True, debug="not_busy") # wait while busy - - # can go straight to reset. - yield port1.is_st_i.eq(0) # end - yield port1.addr.ok.eq(0) # set !ok - yield port1.is_dcbz_i.eq(0) # reset dcbz too - +# copy of pi_st removed def pi_ld(port1, addr, datalen, msr_pr=0): diff --git a/src/soc/experiment/test/test_dcbz_pi.py b/src/soc/experiment/test/test_dcbz_pi.py index ccc49a63..45b87728 100644 --- a/src/soc/experiment/test/test_dcbz_pi.py +++ b/src/soc/experiment/test/test_dcbz_pi.py @@ -11,7 +11,7 @@ from random import randint, seed from nmigen.sim import Simulator, Delay, Settle from nmutil.util import wrap -from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, pi_dcbz +from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst from soc.config.test.test_loadstore import TestMemPspec from soc.config.loadstore import ConfigMemoryPortInterface @@ -129,7 +129,7 @@ def _test_dcbz_addr_100e0(dut, mem): assert ld_data == 0xf553b658ba7e1f51 print("do_dcbz ===============") - yield from pi_dcbz(pi, addr, msr_pr=0) + yield from pi_st(pi, addr, data, 8, msr_pr=0, is_dcbz=1) print("done_dcbz ===============") yield -- 2.30.2