From 66bb32ed895798b249d816374da51d3628a5c5b0 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Mon, 20 Jul 2020 12:41:46 +0200 Subject: [PATCH] Use PinsN when possible (fixes #27) --- examples/ecpix5_85.py | 6 +++--- examples/headless-ecpix5.py | 2 +- gram/core/multiplexer.py | 20 +++++++++---------- gram/dfii.py | 22 ++++++++++----------- gram/phy/dfi.py | 18 +++++++---------- gram/phy/ecp5ddrphy.py | 14 ++++++------- gram/phy/fakephy.py | 26 ++++++++++++------------- gram/simulation/icarusecpix5platform.py | 6 +++--- gram/simulation/simsoc.py | 2 +- gram/simulation/simsoctb.v | 6 +++--- gram/test/test_dfii.py | 12 ++++++------ libgram/src/dfii.c | 8 ++++---- libgram/src/dfii.h | 2 +- 13 files changed, 70 insertions(+), 74 deletions(-) diff --git a/examples/ecpix5_85.py b/examples/ecpix5_85.py index 9b0bdc9..01a8439 100644 --- a/examples/ecpix5_85.py +++ b/examples/ecpix5_85.py @@ -64,9 +64,9 @@ class _ECPIX5Platform(LatticeECP5Platform): Subsignal("clk", Pins("H3", dir="o")), #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")), Subsignal("clk_en", Pins("P1", dir="o")), - Subsignal("we_n", Pins("R3", dir="o")), - Subsignal("ras_n", Pins("T3", dir="o")), - Subsignal("cas_n", Pins("P2", dir="o")), + Subsignal("we", PinsN("R3", dir="o")), + Subsignal("ras", PinsN("T3", dir="o")), + Subsignal("cas", PinsN("P2", dir="o")), Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")), Subsignal("ba", Pins("U6 N3 N4", dir="o")), #Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")), diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py index 0d61dc8..b010632 100644 --- a/examples/headless-ecpix5.py +++ b/examples/headless-ecpix5.py @@ -33,7 +33,7 @@ class DDR3SoC(SoC, Elaboratable): self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0)) ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, - xdr={"clk":4, "a":4, "ba":4}) + xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "we_n":4, "odt":4, "ras":4, "cas":4, "we":4}) self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins)) self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr) diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py index cc61d09..62bc7b2 100644 --- a/gram/core/multiplexer.py +++ b/gram/core/multiplexer.py @@ -161,10 +161,10 @@ class _Steerer(Elaboratable): return cmd.valid & cmd.ready & getattr(cmd, attr) for i, (phase, sel) in enumerate(zip(dfi.phases, self.sel)): - nranks = len(phase.cs_n) + nranks = len(phase.cs) rankbits = log2_int(nranks) - if hasattr(phase, "reset_n"): - m.d.comb += phase.reset_n.eq(1) + if hasattr(phase, "reset"): + m.d.comb += phase.reset.eq(0) m.d.comb += phase.clk_en.eq(Repl(Signal(reset=1), nranks)) if hasattr(phase, "odt"): # FIXME: add dynamic drive for multi-rank (will be needed for high frequencies) @@ -176,24 +176,24 @@ class _Steerer(Elaboratable): (Array(cmd.ba[-rankbits:] for cmd in commands)[sel])) if i == 0: # Select all ranks on refresh. with m.If(sel == STEER_REFRESH): - m.d.sync += phase.cs_n.eq(0) + m.d.sync += phase.cs.eq(1) with m.Else(): - m.d.sync += phase.cs_n.eq(~rank_decoder.o) + m.d.sync += phase.cs.eq(rank_decoder.o) else: - m.d.sync += phase.cs_n.eq(~rank_decoder.o) + m.d.sync += phase.cs.eq(rank_decoder.o) m.d.sync += phase.bank.eq(Array(cmd.ba[:-rankbits] for cmd in commands)[sel]) else: m.d.sync += [ - phase.cs_n.eq(0), + phase.cs.eq(1), phase.bank.eq(Array(cmd.ba[:] for cmd in commands)[sel]), ] m.d.sync += [ phase.address.eq(Array(cmd.a for cmd in commands)[sel]), - phase.cas_n.eq(~Array(valid_and(cmd, "cas") for cmd in commands)[sel]), - phase.ras_n.eq(~Array(valid_and(cmd, "ras") for cmd in commands)[sel]), - phase.we_n.eq(~Array(valid_and(cmd, "we") for cmd in commands)[sel]) + phase.cas.eq(Array(valid_and(cmd, "cas") for cmd in commands)[sel]), + phase.ras.eq(Array(valid_and(cmd, "ras") for cmd in commands)[sel]), + phase.we.eq(Array(valid_and(cmd, "we") for cmd in commands)[sel]) ] rddata_ens = Array(valid_and(cmd, "is_read") for cmd in commands) diff --git a/gram/dfii.py b/gram/dfii.py index 5b9664c..f3e9884 100644 --- a/gram/dfii.py +++ b/gram/dfii.py @@ -36,17 +36,17 @@ class PhaseInjector(Elaboratable): with m.If(self._command_issue.w_stb): m.d.comb += [ - self._phase.cs_n.eq(Repl(value=~self._command.w_data[0], count=len(self._phase.cs_n))), - self._phase.we_n.eq(~self._command.w_data[1]), - self._phase.cas_n.eq(~self._command.w_data[2]), - self._phase.ras_n.eq(~self._command.w_data[3]), + self._phase.cs.eq(Repl(value=self._command.w_data[0], count=len(self._phase.cs))), + self._phase.we.eq(self._command.w_data[1]), + self._phase.cas.eq(self._command.w_data[2]), + self._phase.ras.eq(self._command.w_data[3]), ] with m.Else(): m.d.comb += [ - self._phase.cs_n.eq(Repl(value=1, count=len(self._phase.cs_n))), - self._phase.we_n.eq(1), - self._phase.cas_n.eq(1), - self._phase.ras_n.eq(1), + self._phase.cs.eq(Repl(value=0, count=len(self._phase.cs))), + self._phase.we.eq(0), + self._phase.cas.eq(0), + self._phase.ras.eq(0), ] with m.If(self._phase.rddata_valid): @@ -65,7 +65,7 @@ class DFIInjector(Elaboratable): self.slave = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) self.master = dfi.Interface(addressbits, bankbits, nranks, databits, nphases) - self._control = csr_bank.csr(4, "w") # sel, clk_en, odt, reset_n + self._control = csr_bank.csr(4, "w") # sel, clk_en, odt, reset self._phases = [] for n, phase in enumerate(self._inti.phases): @@ -87,7 +87,7 @@ class DFIInjector(Elaboratable): for phase in self._inti.phases] m.d.comb += [phase.odt[i].eq(self._control.w_data[2]) for phase in self._inti.phases if hasattr(phase, "odt")] - m.d.comb += [phase.reset_n.eq(self._control.w_data[3]) - for phase in self._inti.phases if hasattr(phase, "reset_n")] + m.d.comb += [phase.reset.eq(self._control.w_data[3]) + for phase in self._inti.phases if hasattr(phase, "reset")] return m diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py index 13ae1cf..7e58b99 100644 --- a/gram/phy/dfi.py +++ b/gram/phy/dfi.py @@ -12,14 +12,14 @@ def phase_description(addressbits, bankbits, nranks, databits): # cmd description ("address", addressbits, DIR_FANOUT), ("bank", bankbits, DIR_FANOUT), - ("cas_n", 1, DIR_FANOUT), - ("cs_n", nranks, DIR_FANOUT), - ("ras_n", 1, DIR_FANOUT), - ("we_n", 1, DIR_FANOUT), + ("cas", 1, DIR_FANOUT), + ("cs", nranks, DIR_FANOUT), + ("ras", 1, DIR_FANOUT), + ("we", 1, DIR_FANOUT), ("clk_en", nranks, DIR_FANOUT), ("odt", nranks, DIR_FANOUT), - ("reset_n", 1, DIR_FANOUT), - ("act_n", 1, DIR_FANOUT), + ("reset", 1, DIR_FANOUT), + ("act", 1, DIR_FANOUT), # wrdata description ("wrdata", databits, DIR_FANOUT), ("wrdata_en", 1, DIR_FANOUT), @@ -38,11 +38,7 @@ class Interface: p = Record(phase_description( addressbits, bankbits, nranks, databits)) self.phases += [p] - p.cas_n.reset = 1 - p.cs_n.reset = (2**nranks-1) - p.ras_n.reset = 1 - p.we_n.reset = 1 - p.act_n.reset = 1 + p.reset.reset = 1 def connect(self, target): if not isinstance(target, Interface): diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 7d6f7dd..9f76e34 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -106,7 +106,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): addressbits = len(self.pads.a.o0) bankbits = len(self.pads.ba.o0) - nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o) + nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0) databits = len(self.pads.dq.io) self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4) @@ -114,7 +114,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): tck = 2/(2*2*self._sys_clk_freq) nphases = 2 databits = len(self.pads.dq.io) - nranks = 1 if not hasattr(self.pads, "cs_n") else len(self.pads.cs_n.o) + nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0) cl, cwl = get_cl_cw("DDR3", tck) cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) @@ -198,11 +198,11 @@ class ECP5DDRPHY(Peripheral, Elaboratable): self.pads.ba.o3[i].eq(dfi.phases[1].bank[i]), ] - controls = ["ras_n", "cas_n", "we_n", "clk_en", "odt"] - if hasattr(self.pads, "reset_n"): - controls.append("reset_n") - if hasattr(self.pads, "cs_n"): - controls.append("cs_n") + controls = ["ras", "cas", "we", "clk_en", "odt"] + if hasattr(self.pads, "reset"): + controls.append("reset") + if hasattr(self.pads, "cs"): + controls.append("cs") for name in controls: m.d.comb += [ getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")), diff --git a/gram/phy/fakephy.py b/gram/phy/fakephy.py index 3d11371..d1c4885 100644 --- a/gram/phy/fakephy.py +++ b/gram/phy/fakephy.py @@ -129,16 +129,16 @@ class DFIPhaseModel(Elaboratable): def elaborate(self, platform): m = Module() - with m.If(~self.phase.cs_n & ~self.phase.ras_n & self.phase.cas_n): + with m.If(self.phase.cs & self.phase.ras & ~self.phase.cas): m.d.comb += [ - self.activate.eq(self.phase.we_n), - self.precharge.eq(~self.phase.we_n), + self.activate.eq(~self.phase.we), + self.precharge.eq(self.phase.we), ] - with m.If(~self.phase.cs_n & self.phase.ras_n & ~self.phase.cas_n): + with m.If(self.phase.cs & ~self.phase.ras & self.phase.cas): m.d.comb += [ - self.write.eq(~self.phase.we_n), - self.read.eq(self.phase.we_n), + self.write.eq(self.phase.we), + self.read.eq(~self.phase.we), ] return m @@ -163,12 +163,12 @@ class TimingRule: class DFITimingsChecker(Elaboratable): CMDS = [ # Name, cs & ras & cas & we value - ("PRE", "0010"), # Precharge - ("REF", "0001"), # Self refresh - ("ACT", "0011"), # Activate - ("RD", "0101"), # Read - ("WR", "0100"), # Write - ("ZQCS", "0110"), # ZQCS + ("PRE", "1101"), # Precharge + ("REF", "1110"), # Self refresh + ("ACT", "1100"), # Activate + ("RD", "1010"), # Read + ("WR", "1011"), # Write + ("ZQCS", "1001"), # ZQCS ] RULES = [ @@ -291,7 +291,7 @@ class DFITimingsChecker(Elaboratable): ps = Signal().like(cnt) m.d.comb += ps.eq((cnt + np)*int(self.timings["tCK"])) state = Signal(4) - m.d.comb += state.eq(Cat(phase.we_n, phase.cas_n, phase.ras_n, phase.cs_n)) + m.d.comb += state.eq(Cat(phase.we, phase.cas, phase.ras, phase.cs)) all_banks = Signal() m.d.comb += all_banks.eq( diff --git a/gram/simulation/icarusecpix5platform.py b/gram/simulation/icarusecpix5platform.py index 9296f45..7ab9250 100644 --- a/gram/simulation/icarusecpix5platform.py +++ b/gram/simulation/icarusecpix5platform.py @@ -68,9 +68,9 @@ class IcarusECPIX5Platform(LatticeECP5Platform): Subsignal("clk", Pins("H3", dir="o")), #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")), Subsignal("clk_en", Pins("P1", dir="o")), - Subsignal("we_n", Pins("R3", dir="o")), - Subsignal("ras_n", Pins("T3", dir="o")), - Subsignal("cas_n", Pins("P2", dir="o")), + Subsignal("we", PinsN("R3", dir="o")), + Subsignal("ras", PinsN("T3", dir="o")), + Subsignal("cas", PinsN("P2", dir="o")), Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")), Subsignal("ba", Pins("U6 N3 N4", dir="o")), #Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")), diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py index a151897..abfded2 100644 --- a/gram/simulation/simsoc.py +++ b/gram/simulation/simsoc.py @@ -30,7 +30,7 @@ class DDR3SoC(SoC, Elaboratable): self._arbiter.add(self.ub.bus) ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, - xdr={"clk":4, "a":4, "ba":4}) + xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "we_n":4, "odt":4, "ras":4, "cas":4, "we":4}) self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins)) self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr) diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v index e90c19e..5c25c2f 100644 --- a/gram/simulation/simsoctb.v +++ b/gram/simulation/simsoctb.v @@ -79,9 +79,9 @@ module simsoctb; .ddr3_0__dqs__io(dram_dqs), .ddr3_0__clk__io(dram_ck), .ddr3_0__clk_en__io(dram_cke), - .ddr3_0__we_n__io(dram_we_n), - .ddr3_0__ras_n__io(dram_ras_n), - .ddr3_0__cas_n__io(dram_cas_n), + .ddr3_0__we__io(dram_we_n), + .ddr3_0__ras__io(dram_ras_n), + .ddr3_0__cas__io(dram_cas_n), .ddr3_0__a__io(dram_a), .ddr3_0__ba__io(dram_ba), .ddr3_0__dm__io(dram_dm), diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py index 6bb238e..195c917 100644 --- a/gram/test/test_dfii.py +++ b/gram/test/test_dfii.py @@ -46,10 +46,10 @@ class PhaseInjectorTestCase(FHDLTestCase): m, dfi, csrhost = self.generate_phaseinjector() def process(): - self.assertTrue((yield dfi.phases[0].cas_n)) - self.assertTrue((yield dfi.phases[0].ras_n)) - self.assertTrue((yield dfi.phases[0].we_n)) - self.assertTrue((yield dfi.phases[0].act_n)) + self.assertFalse((yield dfi.phases[0].cas)) + self.assertFalse((yield dfi.phases[0].ras)) + self.assertFalse((yield dfi.phases[0].we)) + self.assertFalse((yield dfi.phases[0].act)) self.assertFalse((yield dfi.phases[0].wrdata_mask)) self.assertFalse((yield dfi.phases[0].rddata_en)) self.assertFalse((yield dfi.phases[0].wrdata_en)) @@ -162,10 +162,10 @@ class DFIInjectorTestCase(FHDLTestCase): def process(): yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 3), sel=0xF) yield - self.assertTrue((yield dut.master.phases[0].reset_n)) + self.assertTrue((yield dut.master.phases[0].reset)) yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF) yield - self.assertFalse((yield dut.master.phases[0].reset_n)) + self.assertFalse((yield dut.master.phases[0].reset)) runSimulation(m, process, "test_dfiinjector.vcd") diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c index d64e872..2909065 100644 --- a/libgram/src/dfii.c +++ b/libgram/src/dfii.c @@ -15,9 +15,9 @@ static void dfii_setcontrol(struct gramCtx *ctx, uint8_t val) { void dfii_setsw(struct gramCtx *ctx, bool software_control) { if (software_control) { - dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT); } else { - dfii_setcontrol(ctx, DFII_CONTROL_SEL); + dfii_setcontrol(ctx, DFII_CONTROL_SEL|DFII_CONTROL_RESET); } } @@ -60,13 +60,13 @@ void dfii_initseq(struct gramCtx *ctx) { /* Release reset */ dfii_set_p0_address(ctx, 0x0); dfii_set_p0_baddress(ctx, 0); - dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + dfii_setcontrol(ctx, DFII_CONTROL_ODT); cdelay(50000); /* Bring CKE high */ dfii_set_p0_address(ctx, 0x0); dfii_set_p0_baddress(ctx, 0); - dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT); cdelay(10000); /* Load Mode Register 2, CWL=5 */ diff --git a/libgram/src/dfii.h b/libgram/src/dfii.h index 1d53306..f57c360 100644 --- a/libgram/src/dfii.h +++ b/libgram/src/dfii.h @@ -6,7 +6,7 @@ #define DFII_CONTROL_SEL (1 << 0) #define DFII_CONTROL_CKE (1 << 1) #define DFII_CONTROL_ODT (1 << 2) -#define DFII_CONTROL_RESET_N (1 << 3) +#define DFII_CONTROL_RESET (1 << 3) #define DFII_COMMAND_CS (1 << 0) #define DFII_COMMAND_WE (1 << 1) -- 2.30.2