From 66c6f3b78bbf8a804219e12a105c9205cf8154fc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 18 Oct 2018 18:14:36 +0100 Subject: [PATCH] forgot to set clroffset --- riscv/processor.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index d87da25..4431dcd 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -375,11 +375,12 @@ void processor_t::set_csr(int which, reg_t val) // lower 16 bits go into even, upper into odd... state.sv_csrs[tbidx].u = get_field(val, 0xffff); state.sv_csrs[tbidx+1].u = get_field(val, 0xffff<<16); - int clroffset = 0; + int clroffset = 2; if (xlen == 64) { state.sv_csrs[tbidx+2].u = get_field(val, 0xffff<<32); state.sv_csrs[tbidx+3].u = get_field(val, 0xffff<<48); + clroffset = 4; } // clear out all CSRs above the one(s) being set: this ensures that // when it comes to context-switching, it's clear what needs to be saved @@ -435,11 +436,12 @@ void processor_t::set_csr(int which, reg_t val) int tbidx = (which - CSR_SVPREDCFG0) * 2; state.sv_pred_csrs[tbidx].u = get_field(val, 0xffff); state.sv_pred_csrs[tbidx+1].u = get_field(val, 0xffff0000); - int clroffset = 0; + int clroffset = 2; if (xlen == 64) { state.sv_pred_csrs[tbidx+2].u = get_field(val, 0xffff<<32); state.sv_pred_csrs[tbidx+3].u = get_field(val, 0xffff<<48); + clroffset = 4; } for (int i = tbidx+clroffset; i < 16; i++) { -- 2.30.2