From 66db5471307c031ce95e84aba93150794da0fa1f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 May 2020 18:13:38 +0100 Subject: [PATCH] add comment about CMP swapping --- src/soc/alu/main_stage.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index ad4e8e87..3d5a3f45 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -48,6 +48,10 @@ class ALUMainStage(PipeModBase): with m.Switch(self.i.ctx.op.insn_type): #### CMP, CMPL #### with m.Case(InternalOp.OP_CMP): + # this is supposed to be inverted (b-a, not a-b) + # however we have a trick: instead of adding either 2x 64-bit + # MUXes to invert a and b, or messing with a 64-bit output, + # swap +ve and -ve test in the *output* stage using an XOR gate comb += o.eq(add_output[1:-1]) #### add #### -- 2.30.2