From 66e327517b10a19690a470c8dccfa363ba061022 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 2 Apr 2020 12:54:47 +0200 Subject: [PATCH] aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits invalid RTL. For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits into that mode) and x being SImode; for non-CONST_INT y it zero extends y into SImode and compares that against x, for CONST_INT y it zero extends y into SImode. The problem is that when the zero extended constant isn't usable directly, it forces it into a REG, but with y_mode mode, and then compares against y. That is wrong, because it should force it into a SImode REG and compare that way. 2020-04-02 Jakub Jelinek PR target/94435 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode. * gcc.target/aarch64/pr94435.c: New test. --- gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6df3a17a645..1f20cbd8c73 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-04-02 Jakub Jelinek + + PR target/94435 + * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For + y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode. + 2020-04-02 Srinath Parvathaneni PR target/94317 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1249f46ed88..16940b44c82 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-04-02 Jakub Jelinek + + PR target/94435 + * gcc.target/aarch64/pr94435.c: New test. + 2020-04-02 Srinath Parvathaneni PR target/94317 -- 2.30.2