From 67005633e246e47683b11e13f08afb788bc9de02 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 23 Apr 2019 23:01:38 +0200 Subject: [PATCH] Add specify support to README Signed-off-by: Clifford Wolf --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index 913777f2e..d21d60c97 100644 --- a/README.md +++ b/README.md @@ -424,6 +424,11 @@ Verilog Attributes and non-standard features in an unconditional context (only if/case statements on parameters and constant values). The intended use for this is synthesis-time DRC. +- There is limited support for converting specify .. endspecify statements to + special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in + blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this + functionality. (By default specify .. endspecify blocks are ignored.) + Non-standard or SystemVerilog features for formal verification ============================================================== -- 2.30.2