From 671dfa5d8c1074dc2a5cd3a3a177a712101f2252 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 22:07:06 +0100 Subject: [PATCH] bug #424 - 32/64 bit is a *global* flag not a per-op one when it comes to setting CR0 --- src/soc/fu/common_output_stage.py | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index fb1310ca..bc89359d 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -26,11 +26,14 @@ class CommonOutputStage(PipeModBase): comb += o.eq(self.i.o.data) # ... no inversion # target register if 32-bit is only the 32 LSBs + # XXX ah. right. this needs to be done only if the *mode* is 32-bit + # see https://bugs.libre-soc.org/show_bug.cgi?id=424 target = Signal(64, reset_less=True) - with m.If(op.is_32bit): - comb += target.eq(o[:32]) - with m.Else(): - comb += target.eq(o) + #with m.If(op.is_32bit): + # comb += target.eq(o[:32]) + #with m.Else(): + # comb += target.eq(o) + comb += target.eq(o) # carry-out only if actually present in this input spec # (note: MUL and DIV do not have it, but ALU and Logical do) @@ -55,13 +58,19 @@ class CommonOutputStage(PipeModBase): comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP) comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB) - with m.If(op.is_32bit): - comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB - with m.Else(): - comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB + # nope - if *processor* mode is 32-bit + #with m.If(op.is_32bit): + # comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB + #with m.Else(): + # comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB + comb += msb_test.eq(target[-1]) # 64-bit MSB comb += is_nzero.eq(target.bool()) - comb += is_positive.eq(is_nzero & ~msb_test) - comb += is_negative.eq(is_nzero & msb_test) + with m.If(is_cmp): # invert pos/neg tests + comb += is_positive.eq(msb_test) + comb += is_negative.eq(is_nzero & ~msb_test) + with m.Else(): + comb += is_negative.eq(msb_test) + comb += is_positive.eq(is_nzero & ~msb_test) with m.If(is_cmpeqb): comb += cr0.eq(self.i.cr0.data) -- 2.30.2