From 6747b127afa0c9ff4be3e147fbadd1be4e2bf491 Mon Sep 17 00:00:00 2001 From: Michael LeBeane Date: Thu, 7 Jun 2018 16:49:26 -0400 Subject: [PATCH] arch-gcn3: Fix VOP2 dissasembly prints VOP2 prints VSRC1 register index as hex instead of decimal if the instruction contains a literal operand. This patch resets the format specifiers in the stream to print the register correctly. Change-Id: Icc7e6588b3c5af545be6590ce412460e72df253f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29936 Tested-by: kokoro Reviewed-by: Anthony Gutierrez Maintainer: Anthony Gutierrez --- src/arch/gcn3/insts/op_encodings.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/gcn3/insts/op_encodings.cc b/src/arch/gcn3/insts/op_encodings.cc index 2eb404253..fe501f215 100644 --- a/src/arch/gcn3/insts/op_encodings.cc +++ b/src/arch/gcn3/insts/op_encodings.cc @@ -763,7 +763,8 @@ namespace Gcn3ISA << extData.imm_u32 << ", "; } - dis_stream << "v" << instData.VSRC1; + dis_stream << std::resetiosflags(std::ios_base::basefield) << "v" + << instData.VSRC1; if (readsVCC()) dis_stream << ", vcc"; -- 2.30.2