From 6773e9193ea719c994c6fb82c04810410a787c7e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 3 Aug 2022 22:40:52 -0700 Subject: [PATCH] split out sim_util.write_il from sim_util.do_sim --- src/nmutil/sim_util.py | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/nmutil/sim_util.py b/src/nmutil/sim_util.py index 373f4b9..d5678c2 100644 --- a/src/nmutil/sim_util.py +++ b/src/nmutil/sim_util.py @@ -20,21 +20,26 @@ def hash_256(v): ) -@contextmanager -def do_sim(test_case, dut, traces=(), ports=None): +def write_il(test_case, dut, ports=()): # only elaborate once, cuz users' stupid code breaks if elaborating twice dut = Fragment.get(dut, platform=None) if "sync" not in dut.domains: dut.add_domains(ClockDomain("sync")) - sim = Simulator(dut) path = get_test_path(test_case, "sim_test_out") path.parent.mkdir(parents=True, exist_ok=True) - vcd_path = path.with_suffix(".vcd") - gtkw_path = path.with_suffix(".gtkw") il_path = path.with_suffix(".il") + il_path.write_text(convert(dut, ports=ports), encoding="utf-8") + return dut, path + + +@contextmanager +def do_sim(test_case, dut, traces=(), ports=None): if ports is None: ports = traces - il_path.write_text(convert(dut, ports=ports), encoding="utf-8") + dut, path = write_il(test_case, dut, ports) + sim = Simulator(dut) + vcd_path = path.with_suffix(".vcd") + gtkw_path = path.with_suffix(".gtkw") with sim.write_vcd(vcd_path.open("wt", encoding="utf-8"), gtkw_path.open("wt", encoding="utf-8"), traces=traces): -- 2.30.2