From 679d13c99c68f545933aecadd63de07de2d3d902 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 6 May 2013 09:56:10 +0200 Subject: [PATCH] another attempt at fixing clock routing issues --- build.py | 2 -- verilog/m1crg/m1crg.v | 10 ++++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/build.py b/build.py index a87c8a30..73bd7720 100755 --- a/build.py +++ b/build.py @@ -18,8 +18,6 @@ TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; """, clk50=platform.lookup_request("clk50")) platform.add_platform_command(""" -INST "m1crg/pll" LOC="PLL_ADV_X0Y1"; -INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6"; INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3"; diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v index 596b00d4..10e30e04 100644 --- a/verilog/m1crg/m1crg.v +++ b/verilog/m1crg/m1crg.v @@ -209,6 +209,12 @@ BUFG bufg_x1( .O(sys_clk) ); +wire clk50g; +BUFG bufg_50( + .I(pllout4), + .O(clk50g) +); + wire clk2x_off; BUFG bufg_x2_offclk( .I(pllout5), @@ -253,7 +259,7 @@ ODDR2 #( * Ethernet PHY */ -always @(posedge pllout4) +always @(posedge clk50g) eth_phy_clk_pad <= ~eth_phy_clk_pad; /* Let the synthesizer insert the appropriate buffers */ @@ -277,7 +283,7 @@ DCM_CLKGEN #( .CLKFX180(), .CLKFXDV(), .STATUS(), - .CLKIN(pllout4), + .CLKIN(clk50g), .FREEZEDCM(1'b0), .PROGCLK(vga_progclk), .PROGDATA(vga_progdata), -- 2.30.2