From 67a04feb918521da7e4ca7e07f8605507ee0e761 Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 20 Jul 2020 17:13:27 -0300
Subject: [PATCH] Remove extra yield from test case.

Seems pysim is correct, after all. There seems to be some
strange interaction between cxxrtl and python.
---
 src/soc/experiment/alu_fsm.py | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index b3ab5b17..f3b67264 100644
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -240,9 +240,6 @@ def test_shifter():
             yield
         # read result
         result = yield dut.n.data_o.data
-
-        # must leave ready_i valid for 1 cycle, ready_i to register for 1 cycle
-        yield
         # negate n.ready_i
         yield dut.n.ready_i.eq(0)
         # check result
-- 
2.30.2