From 67b0ce2578f8c7ade43e8c4e817e4bf4225e78fb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 2 Feb 2014 21:27:26 +0100 Subject: [PATCH] Only generate write-enable $and if WE is not constant 1 in memory_map --- passes/memory/memory_map.cc | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 45c3933c3..9f2b6994c 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -273,22 +273,25 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) module->wires[w->name] = w; c->connections["\\Y"] = RTLIL::SigSpec(w); - c = new RTLIL::Cell; - c->name = genid(cell->name, "$wren", i, "", j); - c->type = "$and"; - c->parameters["\\A_SIGNED"] = RTLIL::Const(0); - c->parameters["\\B_SIGNED"] = RTLIL::Const(0); - c->parameters["\\A_WIDTH"] = RTLIL::Const(1); - c->parameters["\\B_WIDTH"] = RTLIL::Const(1); - c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); - c->connections["\\A"] = RTLIL::SigSpec(w); - c->connections["\\B"] = wr_en; - module->cells[c->name] = c; + if (wr_en != RTLIL::SigSpec(1, 1)) + { + c = new RTLIL::Cell; + c->name = genid(cell->name, "$wren", i, "", j); + c->type = "$and"; + c->parameters["\\A_SIGNED"] = RTLIL::Const(0); + c->parameters["\\B_SIGNED"] = RTLIL::Const(0); + c->parameters["\\A_WIDTH"] = RTLIL::Const(1); + c->parameters["\\B_WIDTH"] = RTLIL::Const(1); + c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); + c->connections["\\A"] = RTLIL::SigSpec(w); + c->connections["\\B"] = wr_en; + module->cells[c->name] = c; - w = new RTLIL::Wire; - w->name = genid(cell->name, "$wren", i, "", j, "$y"); - module->wires[w->name] = w; - c->connections["\\Y"] = RTLIL::SigSpec(w); + w = new RTLIL::Wire; + w->name = genid(cell->name, "$wren", i, "", j, "$y"); + module->wires[w->name] = w; + c->connections["\\Y"] = RTLIL::SigSpec(w); + } c = new RTLIL::Cell; c->name = genid(cell->name, "$wrmux", i, "", j); -- 2.30.2