From 67be62a957c565bfa03f084c8f110d65ca14196b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 Nov 2019 12:04:11 -0800 Subject: [PATCH] clkpart to analyse async flops too --- passes/hierarchy/clkpart.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc index b79625540..15a5328b9 100644 --- a/passes/hierarchy/clkpart.cc +++ b/passes/hierarchy/clkpart.cc @@ -161,6 +161,14 @@ struct ClkPartPass : public Pass { bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec()); } + else + if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), + ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_))) + { + bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)); + log_assert(!enable_mode); // TODO + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); + } else continue; -- 2.30.2