From 67c9c41f7e566f5604a3e38e7ad402d6b5c80fd8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 17:10:54 -0800
Subject: [PATCH] Move abc9.* constpad entries to Abc9Pass::on_register()

---
 kernel/yosys.cc        | 35 -----------------------------------
 passes/techmap/abc9.cc | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 35 deletions(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6956cbdc3..8190d8902 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -524,41 +524,6 @@ void yosys_setup()
 		PyRun_SimpleString("import sys");
 	#endif
 
-	RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
-	RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
-	RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
-	// Based on ABC's &flow
-	RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
-		/* Round 1 */ \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &dsdb;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &syn2 -m -R 10; &dsdb;" \
-		"&blut -a -K 6;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		/* Round 2 */ \
-		"&st; &sopb;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &dsdb;" \
-		"&unmap; &if {C} {W} {D} {R}; &mfs;" \
-		"&st; &syn2 -m -R 10; &dsdb;" \
-		"&blut -a -K 6;" \
-		"&unmap; &if {C} {W} {D} {R} -v; &mfs";
-	// Based on ABC's &flow2
-	RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
-		/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-		/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-		"&load; &st; &sopb -R 10 -C 4; " \
-		/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-		/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
-		"&load";
-	// Based on ABC's &flow3
-	RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
-		"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
-		"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
-		"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
-		"&mfs";
-
 	Pass::init_register();
 	yosys_design = new RTLIL::Design;
 	yosys_celltypes.setup();
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3fdcc0e5c..3f05494c7 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -735,6 +735,43 @@ clone_lut:
 
 struct Abc9Pass : public Pass {
 	Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
+	void on_register() YS_OVERRIDE
+	{
+		RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
+		RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
+		RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
+		// Based on ABC's &flow
+		RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
+			/* Round 1 */ \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &dsdb;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &syn2 -m -R 10; &dsdb;" \
+			"&blut -a -K 6;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			/* Round 2 */ \
+			"&st; &sopb;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &dsdb;" \
+			"&unmap; &if {C} {W} {D} {R}; &mfs;" \
+			"&st; &syn2 -m -R 10; &dsdb;" \
+			"&blut -a -K 6;" \
+			"&unmap; &if {C} {W} {D} {R} -v; &mfs";
+		// Based on ABC's &flow2
+		RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
+			/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+			/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+			"&load; &st; &sopb -R 10 -C 4; " \
+			/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+			/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
+			"&load";
+		// Based on ABC's &flow3
+		RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
+			"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
+			"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
+			"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
+			"&mfs";
+	}
 	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-- 
2.30.2