From 67d7985d33e655bc759ad6de58409bbb2f572c9c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Aug 2022 12:12:16 +0100 Subject: [PATCH] remove use of sv.lfssh, replace with sv.lfs/els element strided --- src/openpower/decoder/isa/test_caller_svp64_dct.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py index 8541a81e..9a8c1158 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dct.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py @@ -925,7 +925,7 @@ class DCTTestCase(FHDLTestCase): """>>> lst = [# LOAD bit-reversed with half-swap "svshape 8, 1, 1, 6, 0", "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfssh *0, 4(1), 2", + "sv.lfs/els *0, 4(1)", # Inner butterfly, twin +/- MUL-ADD-SUB "svremap 31, 1, 0, 2, 0, 1, 1", "svshape 8, 1, 1, 4, 0", @@ -943,7 +943,7 @@ class DCTTestCase(FHDLTestCase): lst = SVP64Asm( ["addi 1, 0, 0x000", "svshape 8, 1, 1, 6, 0", "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfssh *0, 4(1), 2", + "sv.lfs/els *0, 4(1)", "svremap 31, 1, 0, 2, 0, 1, 1", "svshape 8, 1, 1, 4, 0", "sv.fdmadds *0, *0, *0, *8", @@ -1015,7 +1015,7 @@ class DCTTestCase(FHDLTestCase): """>>> lst = [# LOAD bit-reversed with half-swap "svshape 8, 1, 1, 14, 0", "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfssh *0, 4(1), 2", + "sv.lfs/els *0, 4(1)", # Outer butterfly, iterative sum "svremap 31, 0, 1, 2, 1, 0, 1", "svshape 8, 1, 1, 11, 0", @@ -1033,7 +1033,7 @@ class DCTTestCase(FHDLTestCase): lst = SVP64Asm( ["addi 1, 0, 0x000", "svshape 8, 1, 1, 14, 0", "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfssh *0, 4(1), 2", + "sv.lfs/els *0, 4(1)", "svremap 31, 0, 1, 2, 1, 0, 1", "svshape 8, 1, 1, 11, 0", "sv.fadds *0, *0, *0", -- 2.30.2