From 67da26322fd5faa52b432b55c054e2e6990a732e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 Jul 2020 00:10:10 +0100 Subject: [PATCH] fix unit tests due to change in using pspec --- src/soc/experiment/l0_cache.py | 12 ++++++++++-- src/soc/fu/compunits/compunits.py | 2 +- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index c622ef44..6efde593 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -353,7 +353,11 @@ class TestL0Cache(unittest.TestCase): def test_l0_cache_test_bare_wb(self): - dut = TstL0CacheBuffer(regwid=64, ifacetype='test_bare_wb') + pspec = TestMemPspec(ldst_ifacetype='test_bare_wb', + addr_wid=48, + mask_wid=8, + reg_wid=64) + dut = TstL0CacheBuffer(pspec) vl = rtlil.convert(dut, ports=[])# TODOdut.ports()) with open("test_basic_l0_cache_bare_wb.il", "w") as f: f.write(vl) @@ -363,7 +367,11 @@ class TestL0Cache(unittest.TestCase): def test_l0_cache_testpi(self): - dut = TstL0CacheBuffer(regwid=64, ifacetype='testpi') + pspec = TestMemPspec(ldst_ifacetype='testpi', + addr_wid=48, + mask_wid=8, + reg_wid=64) + dut = TstL0CacheBuffer(pspec) vl = rtlil.convert(dut, ports=[])# TODOdut.ports()) with open("test_basic_l0_cache.il", "w") as f: f.write(vl) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 6a65c6af..bec55b83 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -178,7 +178,7 @@ class AllFunctionUnits(Elaboratable): * type of FU required """ - def __init__(self, pilist=None, addrwid=6): + def __init__(self, pspec, pilist=None, addrwid=6): self.fus = {} for (name, qty, kls) in (('alu', 1, ALUFunctionUnit), ('cr', 1, CRFunctionUnit), -- 2.30.2