From 67ebdcca54381bce6bb068e2405fd7cb85a1a67c Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 21:12:06 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 80dad52b4..3fa0eecc8 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -698,8 +698,17 @@ Put another way: * There must be a JIT binary-translator which either turns PE code into Power ISA code or vice-versa **OR** * The compiler dual-compiles the original source code, and embeds - both a Power binary and a PE binary into the ZOLC Basic Block + both a Power binary and a PE binary into the ZOLC Basic Block **OR** +* All binaries are stored in an Intermediate Representation + (LLVM-IR, SPIR-V) and JIT-compiled on-demand. All of these would work, but it is simpler and a lot less work just to have the PEs -execute the exact same ISA (or a subset of it). +execute the exact same ISA (or a subset of it). If however the +concept of Hybrid PE-Memory Processing were to become a JEDEC Standard, +which would increase adoption and reduce cost, a bit more thought +is required here because ARM or Intel or MIPS might not necessarily +be happy that a Processing Element has to execute Power ISA binaries. +At least the Power ISA is much richer, more powerful, still RISC, +and is an Open Standard, as discussed in a earlier sections. + -- 2.30.2