From 67ee1ea92b4f5db60ebd75235d58a6645ce657f1 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Fri, 27 Mar 2020 11:36:15 +0100 Subject: [PATCH] Re: [libre-riscv-dev] cache SRAM organisation --- 43/f7598a8a37761f98f34d22f7e1536681bd1a77 | 110 ++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 43/f7598a8a37761f98f34d22f7e1536681bd1a77 diff --git a/43/f7598a8a37761f98f34d22f7e1536681bd1a77 b/43/f7598a8a37761f98f34d22f7e1536681bd1a77 new file mode 100644 index 0000000..1133c9d --- /dev/null +++ b/43/f7598a8a37761f98f34d22f7e1536681bd1a77 @@ -0,0 +1,110 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 27 Mar 2020 10:36:24 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHmLf-0003kD-Tj; Fri, 27 Mar 2020 10:36:23 +0000 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) id 1jHmLd-0003k7-DH + for libre-riscv-dev@lists.libre-riscv.org; Fri, 27 Mar 2020 10:36:21 +0000 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id B0B6911C0458 + for ; + Fri, 27 Mar 2020 11:36:20 +0100 (CET) +Message-ID: <9e44930a0332eff507661e617796b9d0674b0e05.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Fri, 27 Mar 2020 11:36:15 +0100 +In-Reply-To: +References: + <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu> + + <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu> + + + + + + <6fbfb2a3258be77f4fce69661b283dc31a683f7b.camel@fibraservi.eu> + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] cache SRAM organisation +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============8086656049151897504==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============8086656049151897504== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-p7q7BDl/EdOk4+ultaEv" + + +--=-p7q7BDl/EdOk4+ultaEv +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:44 [+0000]: +> On Fri, Mar 27, 2020 at 9:25 AM Staf Verhaegen wrote= +: +> > My point is that you will have the same performance for the fixed 5-sta= +ge pipeline running @ 800MHz +>=20 +> no, it won't: it'll be half the clock speed. it won't be double thenumbe= +r of computations: it'll be the exact same number ofcomputations. therefor= +e, half the speed means half the number ofcomputations because the *through= +put* is the same +> when you use "cpufreq-set" to change the clock rate, if the clock rateis = +halved, the computer is twice as slow. + +You are right. + +> yes it's confusing :) + +Yes and no, it is the basic functionality of a pipeline :( +You have the same latency but can have double the number of operations in f= +light. + +greets, +Staf. + + + + +--=-p7q7BDl/EdOk4+ultaEv-- + + + +--===============8086656049151897504== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============8086656049151897504==-- + + + -- 2.30.2