From 680153bd1eefcdd31809fedd9a937bff03853dcf Mon Sep 17 00:00:00 2001
From: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri, 16 Dec 2016 16:26:08 +0000
Subject: [PATCH] [AArch64] Split X-reg UBFIZ into W-reg LSL when possible

	* config/aarch64/aarch64.md: New define_split above bswap<mode>2.

	* gcc.target/aarch64/ubfiz_lsl_1.c: New test.

From-SVN: r243756
---
 gcc/ChangeLog                                  |  4 ++++
 gcc/config/aarch64/aarch64.md                  | 18 ++++++++++++++++++
 gcc/testsuite/ChangeLog                        |  4 ++++
 gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c | 13 +++++++++++++
 4 files changed, 39 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d7f39fcb05e..9aecfdc9d94 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.md: New define_split above bswap<mode>2.
+
 2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64.md: New define_split above insv<mode>.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 078bd8e69a0..6d89e31fdeb 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4439,6 +4439,24 @@
   [(set_attr "type" "bfx")]
 )
 
+;; When the bit position and width of the equivalent extraction add up to 32
+;; we can use a W-reg LSL instruction taking advantage of the implicit
+;; zero-extension of the X-reg.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand")
+			     (match_operand 2 "const_int_operand"))
+		 (match_operand 3 "const_int_operand")))]
+ "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2])
+  && (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3])))
+      == GET_MODE_BITSIZE (SImode)"
+  [(set (match_dup 0)
+	(zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))]
+  {
+    operands[4] = gen_lowpart (SImode, operands[1]);
+  }
+)
+
 (define_insn "bswap<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
         (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))]
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fc73346906c..30f89311da8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/ubfiz_lsl_1.c: New test.
+
 2016-12-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* gcc.target/aarch64/ubfx_lsr_1.c: New test.
diff --git a/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c
new file mode 100644
index 00000000000..d3fd3f234f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL.  */
+
+long long
+f2 (long long x)
+{
+  return (x << 5) & 0xffffffff;
+}
+
+/* { dg-final { scan-assembler "lsl\tw" } } */
+/* { dg-final { scan-assembler-not "ubfiz\tx" } } */
-- 
2.30.2