From 6804797178f4c4c831fa43e94f51fdaaad4641f3 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 20 May 2016 13:55:58 +0200 Subject: [PATCH] re PR target/29756 (SSE intrinsics hard to use without redundant temporaries appearing) PR tree-optimization/29756 gcc.dg/tree-ssa/vector-6.c: Add -Wno-psabi -w to dg-options. Add -msse2 for x86 and -maltivec for powerpc. Use scan-tree-dump-times only on selected targets where V4SImode vectors are known to be supported. From-SVN: r236505 --- gcc/testsuite/ChangeLog | 8 ++++++++ gcc/testsuite/gcc.dg/tree-ssa/vector-6.c | 6 ++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ce47e644ca0..94080ab6921 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2016-05-20 Jakub Jelinek + + PR tree-optimization/29756 + gcc.dg/tree-ssa/vector-6.c: Add -Wno-psabi -w to dg-options. + Add -msse2 for x86 and -maltivec for powerpc. Use scan-tree-dump-times + only on selected targets where V4SImode vectors are known to be + supported. + 2016-05-20 Marc Glisse PR tree-optimization/71079 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c b/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c index 059ef4ec98c..785e5dfe424 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-O -fdump-tree-ccp1" } */ +/* { dg-options "-O -fdump-tree-ccp1 -Wno-psabi -w" } */ +/* { dg-additional-options "-msse2" { target i?86-*-* x86_64-*-* } } */ +/* { dg-additional-options "-maltivec" { target powerpc_altivec_ok } } */ typedef int v4si __attribute__((vector_size (4 * sizeof (int)))); @@ -30,4 +32,4 @@ v4si test4 (v4si v, int i) return v; } -/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 4 "ccp1" } } */ +/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 4 "ccp1" { target { { i?86-*-* x86_64-*-* aarch64*-*-* spu*-*-* } || { powerpc_altivec_ok } } } } } */ -- 2.30.2