From 6828f2a2930ffd8f3ba4a6aee75315972d856a56 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 Apr 2022 17:00:18 +0100 Subject: [PATCH] correct default to zero string not zero int --- src/soc/simple/issuer_verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 1ddc4211..dd7bcc77 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -59,7 +59,7 @@ if __name__ == '__main__': parser.add_argument("--disable-svp64", dest='svp64', action="store_false", help="disable SVP64", default=False) - parser.add_argument("--pc-reset", default=0, + parser.add_argument("--pc-reset", default="0", help="Set PC at reset (default 0)") parser.add_argument("--xlen", default=64, type=int, help="Set register width [default 64]") -- 2.30.2