From 682c6b74227fea89dd39c4788dfd8d095743d997 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 19:33:41 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 9d3f89a1a..d2586208e 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -261,7 +261,8 @@ The question then becomes: with all the duplication of arithmetic operations just to make the registers scalar or vector, why not leverage the *existing* Scalar ISA with some sort of "context" or prefix that augments its behaviour? Make "Scalar instruction" -synonymous with "Scalar instruction" and through contextual +synonymous with "Vector Element instruction" and through nothing +more than contextual augmentation the Scalar ISA *becomes* the Vector ISA. Then, by not having to have any Vector instructions at all, the Instruction Decode -- 2.30.2