From 6865c2aaf1ded2160fd26ce142139c399e21ebe6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 17 Dec 2020 12:41:38 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index bf960b973..4973ff42b 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -2,6 +2,13 @@ * > +# Note about naming + +the original assessment for SVP from 18 months ago concluded that it should be easy for scalar (non SV) instructions to get at the exact same scalar registers when in SVP mode. otherwise scalar v3.0B code needs to restrict itself to a massively truncated subset of the scalar registers numbered 0-31 (only r0, r4, r8...) whuch hugely interferes with ABIs to such an extent that it would compromise SV. + +question: has anything changed about the assessment that was done, which concluded that for scalar SVP regs they should overlap completely with scalar ISA regs? + + # Notes on requirements for bit allocations do not try to jam VL or MAXVL in. go with the flow of 24 bits spare. -- 2.30.2