From 687027a4d55c087c933ef94868ff5450311e98ca Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Mon, 16 May 2011 14:20:19 +0000 Subject: [PATCH] re PR middle-end/27663 (missed-optimization transforming a byte array to unsigned long) PR target/27663 PR target/41076 * config/avr/predicates.md (const_8_16_24_operand): New predicate. * config/avr/avr.md ("*iorqi.byte0", "*iorqi.byte1-3"): New define_insn_and_split patterns. From-SVN: r173792 --- gcc/ChangeLog | 8 ++++++++ gcc/config/avr/avr.md | 39 ++++++++++++++++++++++++++++++++++++ gcc/config/avr/predicates.md | 7 +++++++ 3 files changed, 54 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b8af4fb3ede..8ba223fe60f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2011-05-16 Georg-Johann Lay + + PR target/27663 + PR target/41076 + * config/avr/predicates.md (const_8_16_24_operand): New predicate. + * config/avr/avr.md ("*iorqi.byte0", + "*iorqi.byte1-3"): New define_insn_and_split patterns. + 2011-05-16 Georg-Johann Lay PR target/45099 diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 1ab30332bdb..efe6bb6914f 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -3388,3 +3388,42 @@ clr __zero_reg__" [(set_attr "length" "3") (set_attr "cc" "clobber")]) + + +;; Some combine patterns that try to fix bad code when a value is composed +;; from byte parts like in PR27663. +;; The patterns give some release but the code still is not optimal, +;; in particular when subreg lowering (-fsplit-wide-types) is turned on. +;; That switch obfuscates things here and in many other places. + +(define_insn_and_split "*iorqi.byte0" + [(set (match_operand:HISI 0 "register_operand" "=r") + (ior:HISI + (zero_extend:HISI (match_operand:QI 1 "register_operand" "r")) + (match_operand:HISI 2 "register_operand" "0")))] + "" + "#" + "reload_completed" + [(set (match_dup 3) + (ior:QI (match_dup 3) + (match_dup 1)))] + { + operands[3] = simplify_gen_subreg (QImode, operands[0], mode, 0); + }) + +(define_insn_and_split "*iorqi.byte1-3" + [(set (match_operand:HISI 0 "register_operand" "=r") + (ior:HISI + (ashift:HISI (zero_extend:HISI (match_operand:QI 1 "register_operand" "r")) + (match_operand:QI 2 "const_8_16_24_operand" "n")) + (match_operand:HISI 3 "register_operand" "0")))] + "INTVAL(operands[2]) < GET_MODE_BITSIZE (mode)" + "#" + "&& reload_completed" + [(set (match_dup 4) + (ior:QI (match_dup 4) + (match_dup 1)))] + { + int byteno = INTVAL(operands[2]) / BITS_PER_UNIT; + operands[4] = simplify_gen_subreg (QImode, operands[0], mode, byteno); + }) diff --git a/gcc/config/avr/predicates.md b/gcc/config/avr/predicates.md index 9a3473bf88f..a7cc2ba052f 100755 --- a/gcc/config/avr/predicates.md +++ b/gcc/config/avr/predicates.md @@ -138,3 +138,10 @@ (define_predicate "pseudo_register_operand" (and (match_code "reg") (match_test "!HARD_REGISTER_P (op)"))) + +;; Return true if OP is a constant integer that is either +;; 8 or 16 or 24. +(define_predicate "const_8_16_24_operand" + (and (match_code "const_int") + (match_test "8 == INTVAL(op) || 16 == INTVAL(op) || 24 == INTVAL(op)"))) + -- 2.30.2