From 687051ecbba9e5885d23ab0bf1ac29b95728c94b Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 19 Sep 2019 21:37:43 +1000 Subject: [PATCH] Reformat loadstore1 Signed-off-by: Anton Blanchard --- loadstore1.vhdl | 76 ++++++++++++++++++++++++------------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/loadstore1.vhdl b/loadstore1.vhdl index ac13783..aa3f274 100644 --- a/loadstore1.vhdl +++ b/loadstore1.vhdl @@ -10,55 +10,55 @@ use work.helpers.all; -- We calculate the address in the first cycle entity loadstore1 is - port ( - clk : in std_ulogic; + port ( + clk : in std_ulogic; - l_in : in Decode2ToLoadstore1Type; + l_in : in Decode2ToLoadstore1Type; - l_out : out Loadstore1ToLoadstore2Type - ); + l_out : out Loadstore1ToLoadstore2Type + ); end loadstore1; architecture behave of loadstore1 is - signal r, rin : Loadstore1ToLoadstore2Type; - signal lsu_sum : std_ulogic_vector(63 downto 0); + signal r, rin : Loadstore1ToLoadstore2Type; + signal lsu_sum : std_ulogic_vector(63 downto 0); begin - -- Calculate the address in the first cycle - lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0'); + -- Calculate the address in the first cycle + lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else (others => '0'); - loadstore1_0: process(clk) - begin - if rising_edge(clk) then - r <= rin; - end if; - end process; + loadstore1_0: process(clk) + begin + if rising_edge(clk) then + r <= rin; + end if; + end process; - loadstore1_1: process(all) - variable v : Loadstore1ToLoadstore2Type; - begin - v := r; + loadstore1_1: process(all) + variable v : Loadstore1ToLoadstore2Type; + begin + v := r; - v.valid := l_in.valid; - v.load := l_in.load; - v.data := l_in.data; - v.write_reg := l_in.write_reg; - v.length := l_in.length; - v.byte_reverse := l_in.byte_reverse; - v.sign_extend := l_in.sign_extend; - v.update := l_in.update; - v.update_reg := l_in.update_reg; + v.valid := l_in.valid; + v.load := l_in.load; + v.data := l_in.data; + v.write_reg := l_in.write_reg; + v.length := l_in.length; + v.byte_reverse := l_in.byte_reverse; + v.sign_extend := l_in.sign_extend; + v.update := l_in.update; + v.update_reg := l_in.update_reg; - -- byte reverse stores in the first cycle - if v.load = '0' and l_in.byte_reverse = '1' then - v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length))); - end if; + -- byte reverse stores in the first cycle + if v.load = '0' and l_in.byte_reverse = '1' then + v.data := byte_reverse(l_in.data, to_integer(unsigned(l_in.length))); + end if; - v.addr := lsu_sum; + v.addr := lsu_sum; - -- Update registers - rin <= v; + -- Update registers + rin <= v; - -- Update outputs - l_out <= r; - end process; + -- Update outputs + l_out <= r; + end process; end; -- 2.30.2