From 687f5a5b12b41c4e26c9e5b8d3815c268a7ff7be Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 24 Apr 2015 15:38:11 +0200 Subject: [PATCH] iCE40 bram progress --- techlibs/ice40/brams_map.v | 39 +++++++++++++++++++++-------- techlibs/ice40/tests/test_bram_tb.v | 12 +++++---- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index 0775aac1f..d022def7f 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -20,23 +20,23 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); case ({CLKPOL2, CLKPOL3}) 2'b00: SB_RAM40_4KNRNW #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ ( - .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), - .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) + .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), + .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) ); 2'b01: SB_RAM40_4KNR #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ ( - .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), - .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) + .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), + .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) ); 2'b10: SB_RAM40_4KNW #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ ( - .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), - .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) + .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), + .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) ); 2'b11: SB_RAM40_4K #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ ( - .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), - .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) + .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1), + .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN) ); endcase endgenerate @@ -67,9 +67,26 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); wire [10:0] A1ADDR_11 = A1ADDR; wire [10:0] B1ADDR_11 = B1ADDR; - wire [15:0] A1DATA_16; - wire [15:0] B1DATA_16 = B1DATA; - assign A1DATA = A1DATA_16; + wire [15:0] A1DATA_16, B1DATA_16; + + generate + if (MODE == 1) begin + assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8], + A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]}; + assign B1DATA_16 = {B1DATA[7], B1DATA[7], B1DATA[6], B1DATA[6], B1DATA[5], B1DATA[5], B1DATA[4], B1DATA[4], + B1DATA[3], B1DATA[3], B1DATA[2], B1DATA[2], B1DATA[1], B1DATA[1], B1DATA[0], B1DATA[0]}; + end + if (MODE == 2) begin + assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]}; + assign B1DATA_16 = {B1DATA[3], B1DATA[3], B1DATA[3], B1DATA[3], B1DATA[2], B1DATA[2], B1DATA[2], B1DATA[2], + B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0]}; + end + if (MODE == 3) begin + assign A1DATA = {A1DATA_16[11], A1DATA_16[3]}; + assign B1DATA_16 = {B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], B1DATA[1], + B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0], B1DATA[0]}; + end + endgenerate generate case ({CLKPOL2, CLKPOL3}) diff --git a/techlibs/ice40/tests/test_bram_tb.v b/techlibs/ice40/tests/test_bram_tb.v index b0ac0402a..5d9f92228 100644 --- a/techlibs/ice40/tests/test_bram_tb.v +++ b/techlibs/ice40/tests/test_bram_tb.v @@ -79,14 +79,14 @@ module bram_tb #( clk <= 0; for (i = 0; i < 512; i = i+1) begin - WR_DATA <= xorshift64_state; + WR_DATA = xorshift64_state; xorshift64_next; - WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); + WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]); xorshift64_next; - RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); - WR_EN <= xorshift64_state[55]; + RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]); + WR_EN = xorshift64_state[55] && (WR_ADDR != RD_ADDR); xorshift64_next; #1; clk <= 1; @@ -98,7 +98,9 @@ module bram_tb #( for (j = 0; j < DBITS; j = j+1) expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j]; - $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR"); + $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", + i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, + expected_rd_masked === RD_DATA ? "ok" : "ERROR"); if (expected_rd_masked !== RD_DATA) begin -> error; end end end -- 2.30.2